1 /* 2 * Copyright (c) 2017 Google LLC. 3 * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com> 4 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef _SOC_ATMEL_SAM0_SAMD21_SOC_H_ 10 #define _SOC_ATMEL_SAM0_SAMD21_SOC_H_ 11 12 #ifndef _ASMLANGUAGE 13 14 #define DONT_USE_CMSIS_INIT 15 16 #include <zephyr/types.h> 17 18 #if defined(CONFIG_SOC_SAMD21E15A) 19 #include <samd21e15a.h> 20 #elif defined(CONFIG_SOC_SAMD21E16A) 21 #include <samd21e16a.h> 22 #elif defined(CONFIG_SOC_SAMD21E17A) 23 #include <samd21e17a.h> 24 #elif defined(CONFIG_SOC_SAMD21E18A) 25 #include <samd21e18a.h> 26 #elif defined(CONFIG_SOC_SAMD21G15A) 27 #include <samd21g15a.h> 28 #elif defined(CONFIG_SOC_SAMD21G16A) 29 #include <samd21g16a.h> 30 #elif defined(CONFIG_SOC_SAMD21G17A) 31 #include <samd21g17a.h> 32 #elif defined(CONFIG_SOC_SAMD21G18A) 33 #include <samd21g18a.h> 34 #elif defined(CONFIG_SOC_SAMD21G17AU) 35 #include <samd21g17au.h> 36 #elif defined(CONFIG_SOC_SAMD21G18AU) 37 #include <samd21g18au.h> 38 #elif defined(CONFIG_SOC_SAMD21J15A) 39 #include <samd21j15a.h> 40 #elif defined(CONFIG_SOC_SAMD21J16A) 41 #include <samd21j16a.h> 42 #elif defined(CONFIG_SOC_SAMD21J17A) 43 #include <samd21j17a.h> 44 #elif defined(CONFIG_SOC_SAMD21J18A) 45 #include <samd21j18a.h> 46 #else 47 #error Library does not support the specified device. 48 #endif 49 50 #endif /* _ASMLANGUAGE */ 51 52 #include "adc_fixup_sam0.h" 53 #include "../common/soc_port.h" 54 #include "../common/atmel_sam0_dt.h" 55 56 /** Processor Clock (HCLK) Frequency */ 57 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 58 59 /** Master Clock (MCK) Frequency */ 60 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 61 62 /** Known values */ 63 #define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 64 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 65 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 66 #define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 67 #define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 68 #define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 69 70 /** GCLK1 source frequency selector */ 71 #if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) 72 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 73 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) 74 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 75 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) 76 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 77 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) 78 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 79 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) 80 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ 81 #else 82 #error Unsupported GCLK1 clock source. 83 #endif 84 85 /** Dividers and frequency for GCLK0 */ 86 #define SOC_ATMEL_SAM0_GCLK0_DIV \ 87 (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) 88 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 89 90 /** DFLL48M output frequency */ 91 #define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ 92 (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) 93 94 /** Dividers and frequency for GCLK1 */ 95 #define SOC_ATMEL_SAM0_GCLK1_DIV \ 96 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) 97 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ 98 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) 99 100 /** DFLL48M output multiplier */ 101 #define SOC_ATMEL_SAM0_DFLL48M_MUL \ 102 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) 103 104 /** Frequency for GCLK2 */ 105 #define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 106 107 /** Dividers and frequency for GCLK3 */ 108 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 109 #define SOC_ATMEL_SAM0_GCLK3_DIV \ 110 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) 111 112 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 113 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 114 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 115 116 #endif /* _SOC_ATMEL_SAM0_SAMD21_SOC_H_ */ 117
