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/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_access.h11 * NPCX register bit/field access operations
17 #define FIELD_POS(field) GET_POS_##field argument
18 #define FIELD_SIZE(field) GET_SIZE_##field argument
20 #define GET_FIELD(reg, field) \ argument
21 _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
24 #define SET_FIELD(reg, field, value) \ argument
25 _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
30 #define GET_FIELD_POS(field) \ argument
31 _GET_FIELD_POS_(FIELD_POS(field))
34 #define GET_FIELD_SZ(field) \ argument
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Dreg_def.h172 #define NPCX_DBGCTRL_CCDEV_SEL FIELD(6, 2)
252 #define NPCX_JEN_CTL1_JEN_EN FIELD(0, 4)
253 #define NPCX_JEN_CTL1_JEN_HEN FIELD(4, 4)
259 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
277 #define NPCX_DEV_CTL3_SIO_CLK_SEL FIELD(6, 2)
395 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
398 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
404 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
411 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
415 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
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/Zephyr-latest/include/zephyr/drivers/ethernet/
Deth_nxp_enet_qos.h24 #define _ENET_QOS_REG_FIELD(reg, field) MACRO_MAP_CAT(_PREFIX_UNDERLINE, reg, field, MASK) argument
25 #define _ENET_QOS_REG_MASK(reg, field) CONCAT(ENET_QOS_NAME, _ENET_QOS_REG_FIELD(reg, field)) argument
27 /* Deciphers value of a field from a read value of an enet qos register
30 * field: name of the bit field within the register
33 #define ENET_QOS_REG_GET(reg, field, val) FIELD_GET(_ENET_QOS_REG_MASK(reg, field), val) argument
35 /* Prepares value of a field for a write to an enet qos register
38 * field: name of the bit field within the register
39 * val: value to put into the field
41 #define ENET_QOS_REG_PREP(reg, field, val) FIELD_PREP(_ENET_QOS_REG_MASK(reg, field), val) argument
/Zephyr-latest/dts/bindings/mtd/
Dnxp,imx-flexspi-device.yaml17 CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
18 default corresponds to the reset value of the register field.
25 CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
26 default corresponds to the reset value of the register field.
32 Chip select setup time, in serial clock cycles. See the TCSS field in
34 reset value of the register field.
40 Chip select hold time, in serial clock cycles. See the TCSH field in
42 reset value of the register field.
56 column address. See the CAS field in registers FLASHA1CR0 through
58 field.
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/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483_priv.h41 /** Bit field for source path selection. If set, HV source path is selected, 5V otherwise. */
46 /** Bit field for 5V source switch enabled */
48 /** Bit field for HV source switch enabled */
50 /** Bit field for HV sink switch enabled */
55 /** Bit field for exit dead battery error */
57 /** Bit field for overvoltage fault triggered on 5V source path */
59 /** Bit field for reverse current fault triggered on 5V source path */
61 /** Bit field for short circuit fault triggered on 5V source path */
63 /** Bit field for overcurrent fault triggered on 5V source path */
65 /** Bit field for over temperature protection fault triggered */
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/Zephyr-latest/drivers/sensor/st/vl53l1x/
Dvl53l1_platform_user_data.h45 * @param field ST structure field name
47 * like PALDevDataGet(FilterData.field)[i] or
50 #define VL53L1DevDataGet(Dev, field) (Dev->Data.field) argument
54 * @def VL53L1PALDevDataSet(Dev, field, data)
55 * @brief Set ST private structure @a VL53L1_DevData_t data field
57 * @param field ST structure field name
60 #define VL53L1DevDataSet(Dev, field, data) ((Dev->Data.field) = (data)) argument
/Zephyr-latest/dts/bindings/ethernet/
Dsnps,dwcxgmac.yaml121 This field controls the threshold in the Descriptor cache after
133 This field controls the threshold in the Descriptor cache after
155 BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field.
162 When the mixed_burst enabled, enabling this field has no effect.
169 When the mixed_burst enabled, enabling this field has no effect.
176 When the mixed_burst enabled, enabling this field has no effect.
183 When the mixed_burst enabled, enabling this field has no effect.
190 When the mixed_burst enabled, enabling this field has no effect.
197 When the mixed_burst enabled, enabling this field has no effect.
204 When the mixed_burst enabled, enabling this field has no effect.
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/Zephyr-latest/soc/gd/gd32/common/
Dpinctrl_soc.h33 * - 0-12: GD32_PINMUX_AF bit field.
35 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
38 * - 0-19: GD32_PINMUX_AFIO bit field.
40 * - 26-31: Pin configuration bit field (@ref GD32_PINCFG).
139 * @name GD32 pin configuration bit field mask and positions.
151 /** PUPD field mask. */
153 /** PUPD field position. */
155 /** OTYPE field mask. */
157 /** OTYPE field position. */
159 /** OSPEED field mask. */
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/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpmc_interface.h18 * The requesting agent will write the PMC command op-code into this field.
24 * this field.
29 * Some commands require additional information which is passed into this 8 bit field.
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
52 * code has been written back into the COMMAND field and any data requested has been written into
53 * the DATA field.
73 * HP-SRAM reporting is defined as 10-bit field span across Parameter 1 and 2, unit is 32 KB.
83 * Some commands require additional information which is passed into this 8 bit field.
/Zephyr-latest/dts/bindings/spi/
Dnxp,imx-flexspi.yaml20 Enable AHB bufferable write access by setting register field
26 Enable AHB cacheable read access by setting register field
32 Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].
38 field AHBCR[READADDROPT].
44 setting register field MCR0[COMBINATIONEN].
61 Source clock for flash read. See the RXCLKSRC field in register MCR0.
62 The default corresponds to the reset value of the register field.
74 of this IP. See the RXCLKSRC_B field in register MCR2.
75 The default corresponds to the reset value of the register field.
/Zephyr-latest/dts/bindings/sensor/
Dinvensense,icm42670.yaml23 Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting
44 Maps to GYRO_ODR field in GYRO_CONFIG0 setting
76 Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting
90 Maps to ACCEL_UI_AVG field in ACCEL_CONFIG1 setting.
91 The default corresponds to the reset value of the register field.
105 Maps to ACCEL_UI_FILT_BW field in ACCEL_CONFIG1 setting.
106 The default corresponds to the reset value of the register field.
123 Maps to GYRO_FS_SEL field in GYRO_CONFIG0 setting
136 Maps to GYRO_UI_FILT_BW field in GYRO_CONFIG1 setting.
137 The default corresponds to the reset value of the register field.
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl.h22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
28 /** Mask for the function field. */
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
36 /** Position of the port field. */
38 /** Mask for the port field. */
41 /** Position of the loc field. */
43 /** Mask for the pin field. */
Dgecko-pinctrl-s1.h22 * @name GECKO_pin configuration bit field positions and masks.
26 /** Position of the function field. */
28 /** Mask for the function field. */
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
36 /** Position of the port field. */
38 /** Mask for the port field. */
41 /** Position of the loc field. */
43 /** Mask for the pin field. */
Dnrf-pinctrl.h25 * @name nRF pin configuration bit field positions and masks.
29 /** Position of the function field. */
31 /** Mask for the function field. */
37 /** Position of the clockpin enable field. */
39 /** Mask for the clockpin enable field. */
41 /** Position of the invert field. */
43 /** Mask for the invert field. */
45 /** Position of the low power field. */
47 /** Mask for the low power field. */
49 /** Position of the drive configuration field. */
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/Zephyr-latest/subsys/bluetooth/services/
DKconfig.dis51 The Vendor ID Source field designates which organization assigned the
52 value used in the Vendor ID field value.
62 The Vendor ID field is intended to uniquely identify the vendor of the
63 device. This field is used in conjunction with Vendor ID Source field,
64 which determines which organization assigned the Vendor ID field value.
67 either of which can be used for the Vendor ID field value.
76 The Product ID field is intended to distinguish between different products
77 made by the vendor identified with the Vendor ID field. The vendors
78 themselves manage Product ID field values.
85 The Product Version field is a numeric expression identifying the device
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/Zephyr-latest/drivers/sensor/st/vl53l0x/
Dvl53l0x_platform.h29 /*!< user specific field */
30 uint8_t I2cDevAddr; /* i2c device address user specific field */
47 * @param field ST structure field name
49 * like PALDevDataGet(FilterData.field)[i]
52 #define PALDevDataGet(Dev, field) (Dev->Data.field) argument
55 * @brief Set ST private structure @a VL53L0X_DevData_t data field
57 * @param field ST structure field name
60 #define PALDevDataSet(Dev, field, data) ((Dev->Data.field) = (data)) argument
/Zephyr-latest/tests/drivers/pinctrl/api/src/
Dpinctrl_soc.h19 * @name Test pin configuration bit field positions and masks.
27 /** Position of the pull field. */
29 /** Mask of the pull field. */
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
55 * @param pincfg Pin configuration bit field.
62 * @param pincfg Pin configuration bit field.
/Zephyr-latest/samples/modules/nanopb/
DKconfig12 Configure the simple message buffer field's size.
15 bool "Unlucky number field"
17 Enable the unlucky number field.
/Zephyr-latest/dts/bindings/sdhc/
Despressif,esp32-sdhc-slot.yaml33 using pin control (pinctrl-0 field).
40 using pin control (pinctrl-0 field).
47 using pin control (pinctrl-0 field).
54 using pin control (pinctrl-0 field).
61 using pin control (pinctrl-0 field).
68 using pin control (pinctrl-0 field).
/Zephyr-latest/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/
Dpriv_proxy_net_id.sh13 # the random field of that message.
16 # the random field of that message with the random field
18 # 5. Test passes if the random field of the two Private Net ID advertisements
Dpriv_proxy_node_id.sh15 # the random field of that message. Then it waits for the
21 # the random field of that message with the random field
23 # 5. Test passes if the random field of the two Private Node ID advertisements
/Zephyr-latest/scripts/pylib/twister/twisterlib/
Dquarantine.py10 from dataclasses import dataclass, field
48 scenarios: list[str] = field(default_factory=list)
49 platforms: list[str] = field(default_factory=list)
50 architectures: list[str] = field(default_factory=list)
51 simulations: list[str] = field(default_factory=list)
53 re_scenarios: list = field(default_factory=list)
54 re_platforms: list = field(default_factory=list)
55 re_architectures: list = field(default_factory=list)
56 re_simulations: list = field(default_factory=list)
85 qlist: list[QuarantineElement] = field(default_factory=list)
/Zephyr-latest/subsys/logging/backends/
DKconfig.net25 bool "RFC 5424 chapter 7.1.1 tzKnown field"
32 bool "RFC 5424 chapter 7.1.2 isSynced field"
40 bool "RFC 5424 chapter 7.2.3 software description field"
48 string "RFC 5424 chapter 7.2.3 software field value"
52 User defined value for the software field.
56 bool "RFC 5424 chapter 7.2.4 software version field"
64 bool "RFC 5424 chapter 7.3.1 sequence id field"
72 bool "RFC 5424 chapter 7.3.2 system uptime field"
/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.h41 /* Field mask of SPI transfer format register */
52 /* Field mask of SPI transfer control register */
65 /* Field mask of SPI interrupt enable register */
70 /* Field mask of SPI interrupt status register */
75 /* Field mask of SPI config register */
79 /* Field mask of SPI status register */
83 /* Field mask of SPI control register */
96 /* Field mask of SPI status register */
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h34 * @brief STM32 MCO configuration register bit field
37 * @param shift Position of field within RCC register (= field LSB's index)
38 * @param mask Mask of register field in RCC register
39 * @param val Clock configuration field value (0~0x1F)

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