1# Copyright 2020 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: NXP FlexSPI device
5
6include: [spi-device.yaml, "jedec,jesd216.yaml"]
7
8properties:
9  cs-interval-unit:
10    type: int
11    default: 1
12    enum:
13      - 1
14      - 256
15    description: |
16      Chip select interval units, in serial clock cycles. See the
17      CSINTERVALUNIT field in registers FLASHA1CR0 through FLASHB2CR0. The
18      default corresponds to the reset value of the register field.
19
20  cs-interval:
21    type: int
22    default: 0
23    description: |
24      Minimum interval between chip select deassertion and assertion. See the
25      CSINTERVAL field in registers FLASHA1CR0 through FLASHB2CR0. The
26      default corresponds to the reset value of the register field.
27
28  cs-setup-time:
29    type: int
30    default: 3
31    description: |
32      Chip select setup time, in serial clock cycles. See the TCSS field in
33      registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
34      reset value of the register field.
35
36  cs-hold-time:
37    type: int
38    default: 3
39    description: |
40      Chip select hold time, in serial clock cycles. See the TCSH field in
41      registers FLASHA1CR0 through FLASHB2CR0. The default corresponds to the
42      reset value of the register field.
43
44  data-valid-time:
45    type: int
46    default: 0
47    description: |
48      Data valid time, in nanoseconds. See the registers DLLACR through
49      DLLBCR.
50
51  column-space:
52    type: int
53    default: 0
54    description: |
55      Column address bit width. Set to zero if the flash does not support
56      column address. See the CAS field in registers FLASHA1CR0 through
57      FLASHB2CR0. The default corresponds to the reset value of the register
58      field.
59
60  word-addressable:
61    type: boolean
62    description: |
63      Don't transmit the least significant address bit when the flash is word
64      addressable. See the WA field in registers FLASHA1CR0 through
65      FLASHB2CR0.
66
67  ahb-write-wait-unit:
68    type: int
69    default: 2
70    enum:
71      - 2
72      - 8
73      - 32
74      - 128
75      - 512
76      - 2048
77      - 8192
78      - 32768
79    description: |
80      AHB write wait interval units, in AHB clock cycles. See the AWRWAITUNIT
81      field in registers FLASHA1CR2 through FLASHB2CR2. The default
82      corresponds to the reset value of the register field.
83
84  ahb-write-wait-interval:
85    type: int
86    default: 0
87    description: |
88      Time to wait between AHB triggered command sequences. See the AWRWAIT
89      field in registers FLASHA1CR2 through FLASHB2CR2. The default
90      corresponds to the reset value of the register field.
91