1 /* 2 * Copyright (c) 2022 Andes Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL 7 #include <zephyr/logging/log.h> 8 LOG_MODULE_REGISTER(spi_atcspi200); 9 10 #include "spi_context.h" 11 #include <zephyr/device.h> 12 #include <zephyr/drivers/spi.h> 13 #include <zephyr/drivers/spi/rtio.h> 14 15 #ifdef CONFIG_ANDES_SPI_DMA_MODE 16 #include <zephyr/drivers/dma.h> 17 #endif 18 19 #define REG_TFMAT 0x10 20 #define REG_TCTRL 0x20 21 #define REG_CMD 0x24 22 #define REG_DATA 0x2c 23 #define REG_CTRL 0x30 24 #define REG_STAT 0x34 25 #define REG_INTEN 0x38 26 #define REG_INTST 0x3c 27 #define REG_TIMIN 0x40 28 #define REG_CONFIG 0x7c 29 30 #define SPI_TFMAT(base) (base + REG_TFMAT) 31 #define SPI_TCTRL(base) (base + REG_TCTRL) 32 #define SPI_CMD(base) (base + REG_CMD) 33 #define SPI_DATA(base) (base + REG_DATA) 34 #define SPI_CTRL(base) (base + REG_CTRL) 35 #define SPI_STAT(base) (base + REG_STAT) 36 #define SPI_INTEN(base) (base + REG_INTEN) 37 #define SPI_INTST(base) (base + REG_INTST) 38 #define SPI_TIMIN(base) (base + REG_TIMIN) 39 #define SPI_CONFIG(base) (base + REG_CONFIG) 40 41 /* Field mask of SPI transfer format register */ 42 #define TFMAT_DATA_LEN_OFFSET (8) 43 44 #define TFMAT_CPHA_MSK BIT(0) 45 #define TFMAT_CPOL_MSK BIT(1) 46 #define TFMAT_SLVMODE_MSK BIT(2) 47 #define TFMAT_LSB_MSK BIT(3) 48 #define TFMAT_DATA_MERGE_MSK BIT(7) 49 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8) 50 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16) 51 52 /* Field mask of SPI transfer control register */ 53 #define TCTRL_RD_TCNT_OFFSET (0) 54 #define TCTRL_WR_TCNT_OFFSET (12) 55 #define TCTRL_TRNS_MODE_OFFSET (24) 56 57 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12) 58 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24) 59 60 /* Transfer mode */ 61 #define TRNS_MODE_WRITE_READ (0) 62 #define TRNS_MODE_WRITE_ONLY (1) 63 #define TRNS_MODE_READ_ONLY (2) 64 65 /* Field mask of SPI interrupt enable register */ 66 #define IEN_RX_FIFO_MSK BIT(2) 67 #define IEN_TX_FIFO_MSK BIT(3) 68 #define IEN_END_MSK BIT(4) 69 70 /* Field mask of SPI interrupt status register */ 71 #define INTST_RX_FIFO_INT_MSK BIT(2) 72 #define INTST_TX_FIFO_INT_MSK BIT(3) 73 #define INTST_END_INT_MSK BIT(4) 74 75 /* Field mask of SPI config register */ 76 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0) 77 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4) 78 79 /* Field mask of SPI status register */ 80 #define STAT_RX_NUM_MSK GENMASK(12, 8) 81 #define STAT_TX_NUM_MSK GENMASK(20, 16) 82 83 /* Field mask of SPI control register */ 84 #define CTRL_RX_FIFO_RST_OFFSET (1) 85 #define CTRL_TX_FIFO_RST_OFFSET (2) 86 #define CTRL_RX_THRES_OFFSET (8) 87 #define CTRL_TX_THRES_OFFSET (16) 88 89 #define CTRL_RX_FIFO_RST_MSK BIT(1) 90 #define CTRL_TX_FIFO_RST_MSK BIT(2) 91 #define CTRL_RX_DMA_EN_MSK BIT(3) 92 #define CTRL_TX_DMA_EN_MSK BIT(4) 93 #define CTRL_RX_THRES_MSK GENMASK(12, 8) 94 #define CTRL_TX_THRES_MSK GENMASK(20, 16) 95 96 /* Field mask of SPI status register */ 97 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0) 98 99 #define TX_FIFO_THRESHOLD (1) 100 #define RX_FIFO_THRESHOLD (1) 101 #define MAX_TRANSFER_CNT (512) 102 #define MAX_CHAIN_SIZE (8) 103 104 #define TX_FIFO_SIZE_SETTING(base) \ 105 (sys_read32(SPI_CONFIG(base)) & CFG_TX_FIFO_SIZE_MSK) 106 #define TX_FIFO_SIZE(base) \ 107 (2 << (TX_FIFO_SIZE_SETTING(base) >> 4)) 108 109 #define RX_FIFO_SIZE_SETTING(base) \ 110 (sys_read32(SPI_CONFIG(base)) & CFG_RX_FIFO_SIZE_MSK) 111 #define RX_FIFO_SIZE(base) \ 112 (2 << (RX_FIFO_SIZE_SETTING(base) >> 0)) 113 114 #define TX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_TX_NUM_MSK) 115 #define RX_NUM_STAT(base) (sys_read32(SPI_STAT(base)) & STAT_RX_NUM_MSK) 116 #define GET_TX_NUM(base) (TX_NUM_STAT(base) >> 16) 117 #define GET_RX_NUM(base) (RX_NUM_STAT(base) >> 8) 118
