1 /* 2 * Copyright 2023 Google LLC 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 /** 7 * @file 8 * @brief NX20P3483 PPC registers definitions 9 */ 10 11 #ifndef ZEPHYR_DRIVERS_USBC_PPC_NXP_NX20P3483_PRIV_H_ 12 #define ZEPHYR_DRIVERS_USBC_PPC_NXP_NX20P3483_PRIV_H_ 13 14 #include<zephyr/dt-bindings/usb-c/nxp_nx20p3483.h> 15 16 /** Register address - device id */ 17 #define NX20P3483_REG_DEVICE_ID 0x00 18 /** Bit mask for vendor id */ 19 #define NX20P3483_REG_DEVICE_ID_VENDOR_MASK GENMASK(7, 3) 20 /** Bit mask for version id */ 21 #define NX20P3483_REG_DEVICE_ID_REVISION_MASK GENMASK(2, 0) 22 23 /** Register address - device status */ 24 #define NX20P3483_REG_DEVICE_STATUS 0x01 25 /** Bit mask for device mode */ 26 #define NX20P3483_REG_DEVICE_STATUS_MODE_MASK GENMASK(2, 0) 27 28 /** Value for dead battery mode */ 29 #define NX20P3483_MODE_DEAD_BATTERY 0 30 /** Value for high-voltage sink mode */ 31 #define NX20P3483_MODE_HV_SNK 1 32 /** Value for 5V source mode */ 33 #define NX20P3483_MODE_5V_SRC 2 34 /** Value for high-voltage source mode */ 35 #define NX20P3483_MODE_HV_SRC 3 36 /** Value for standby mode */ 37 #define NX20P3483_MODE_STANDBY 4 38 39 /** Register address - switch control */ 40 #define NX20P3483_REG_SWITCH_CTRL 0x02 41 /** Bit field for source path selection. If set, HV source path is selected, 5V otherwise. */ 42 #define NX20P3483_REG_SWITCH_CTRL_SRC BIT(7) 43 44 /** Register address - switch status */ 45 #define NX20P3483_REG_SWITCH_STATUS 0x03 46 /** Bit field for 5V source switch enabled */ 47 #define NX20P3483_REG_SWITCH_STATUS_5VSRC BIT(2) 48 /** Bit field for HV source switch enabled */ 49 #define NX20P3483_REG_SWITCH_STATUS_HVSRC BIT(1) 50 /** Bit field for HV sink switch enabled */ 51 #define NX20P3483_REG_SWITCH_STATUS_HVSNK BIT(0) 52 53 /** Register address - interrupt1 */ 54 #define NX20P3483_REG_INT1 0x04 55 /** Bit field for exit dead battery error */ 56 #define NX20P3483_REG_INT1_DBEXIT_ERR BIT(7) 57 /** Bit field for overvoltage fault triggered on 5V source path */ 58 #define NX20P3483_REG_INT1_OV_5VSRC BIT(4) 59 /** Bit field for reverse current fault triggered on 5V source path */ 60 #define NX20P3483_REG_INT1_RCP_5VSRC BIT(3) 61 /** Bit field for short circuit fault triggered on 5V source path */ 62 #define NX20P3483_REG_INT1_SC_5VSRC BIT(2) 63 /** Bit field for overcurrent fault triggered on 5V source path */ 64 #define NX20P3483_REG_INT1_OC_5VSRC BIT(1) 65 /** Bit field for over temperature protection fault triggered */ 66 #define NX20P3483_REG_INT1_OTP BIT(0) 67 68 /** Register address - interrupt2*/ 69 #define NX20P3483_REG_INT2 0x05 70 /** Bit field for sink and source routes enabled fault */ 71 #define NX20P3483_REG_INT2_EN_ERR BIT(7) 72 /** Bit field for reverse current fault triggered on HV sink path */ 73 #define NX20P3483_REG_INT2_RCP_HVSNK BIT(6) 74 /** Bit field for short circuit fault triggered on HV sink path */ 75 #define NX20P3483_REG_INT2_SC_HVSNK BIT(5) 76 /** Bit field for overvoltage fault triggered on HV sink path */ 77 #define NX20P3483_REG_INT2_OV_HVSNK BIT(4) 78 /** Bit field for reverse current fault triggered on HV source path */ 79 #define NX20P3483_REG_INT2_RCP_HVSRC BIT(3) 80 /** Bit field for short circuit fault triggered on HV source path */ 81 #define NX20P3483_REG_INT2_SC_HVSRC BIT(2) 82 /** Bit field for overcurrent fault triggered on HV source path */ 83 #define NX20P3483_REG_INT2_OC_HVSRC BIT(1) 84 /** Bit field for overvoltage fault triggered on HV source path */ 85 #define NX20P3483_REG_INT2_OV_HVSRC BIT(0) 86 87 /** Register address - interrupt1 mask */ 88 #define NX20P3483_REG_INT1_MASK 0x06 89 90 /** Register address - interrupt2 mask*/ 91 #define NX20P3483_REG_INT2_MASK 0x07 92 93 /** Register address - OVLO threshold (overvoltage threshold) */ 94 #define NX20P3483_REG_OVLO_THRESHOLD 0x08 95 /** 96 * Bit mask for overvoltage threshold value 97 * Values used in this register are defined as NX20P3483_U_THRESHOLD_* 98 */ 99 #define NX20P3483_REG_OVLO_THRESHOLD_MASK GENMASK(2, 0) 100 101 /* Internal 5V VBUS Switch Current Limit Settings (min) */ 102 #define NX20P3483_ILIM_MASK 0xF 103 104 /** 105 * Register address - HV source switch OCP threshold 106 * Values used in this register are defined as NX20P3483_I_THRESHOLD_* 107 */ 108 #define NX20P3483_REG_HV_SRC_OCP_THRESHOLD 0x09 109 110 /** 111 * Register address - 5V source switch OCP threshold 112 * Values used in this register are defined as NX20P3483_I_THRESHOLD_* 113 */ 114 #define NX20P3483_REG_5V_SRC_OCP_THRESHOLD 0x0A 115 116 /** Register address - device control */ 117 #define NX20P3483_REG_DEVICE_CTRL 0x0B 118 /** Bit field for fast role swap capability activated */ 119 #define NX20P3483_REG_DEVICE_CTRL_FRS_AT BIT(3) 120 /** Bit field for exit dead battery mode */ 121 #define NX20P3483_REG_DEVICE_CTRL_DB_EXIT BIT(2) 122 /** Bit field for VBUS discharge circuit enabled */ 123 #define NX20P3483_REG_DEVICE_CTRL_VBUSDIS_EN BIT(1) 124 /** Bit field for LDO shutdown */ 125 #define NX20P3483_REG_DEVICE_CTRL_LDO_SD BIT(0) 126 127 #endif /* ZEPHYR_DRIVERS_USBC_PPC_NXP_NX20P3483_PRIV_H_ */ 128
