Lines Matching full:field

121       This field controls the threshold in the Descriptor cache after
133       This field controls the threshold in the Descriptor cache after
155       BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4 field.
162       When the mixed_burst enabled, enabling this field has no effect.
169       When the mixed_burst enabled, enabling this field has no effect.
176       When the mixed_burst enabled, enabling this field has no effect.
183       When the mixed_burst enabled, enabling this field has no effect.
190       When the mixed_burst enabled, enabling this field has no effect.
197       When the mixed_burst enabled, enabling this field has no effect.
204       When the mixed_burst enabled, enabling this field has no effect.
223       This field specifies the maximum segment size that must be
224       used while segmenting the Transmit packet. This field is valid
231       This field sets the maximum number of Tx descriptors in the
239       This field sets the maximum number of Rx descriptors in the
247       This field indicates the size of the Rx buffers specified in bytes
263       Buffer1 and Rx Buffer2 sizes are based on RBSZ field. Width of
264       ARBS field is 7 or 6-bits depending on the data bus widths
271       These field indicate the maximum number of beats to be
278       These field indicate the maximum number of beats to be
284       When this field is set, the DMA splits the header and payload in
295       When this field is set, the corresponding channel uses
301       When this field is set, the DMA performs the TCP segmentation
309       When this field is set, it instructs the DMA to process the second
316       This field is used to select the arbitration algorithm for the Rx
323       This field selects the type of ETS algorithm to be applied for
334       Each bit position of this field maps to a queue. there are total 8 queues
339       Receive Queue Mapped to DMA Channel. this field does not have
346       This field indicates the size of the allocated Transmit queues
359           These field control the threshold level of the MTL Tx Queue.
363           field us used only when Transmit Store and Forward is disabled.
382           This field is valid only when the RSF bit is zero. This field is
383           ignored when the RSF field is set to 1.
393       Receive Queue Size. This field indicates the size of the allocated
400       Transmit Store and Forward. When this field is set, the transmission
402       Each bit position of this field maps to a queue. there are total 8 queues
407       Enable Hardware Flow Control. When this field is set, the flow control
409       Each bit position of this field maps to a queue. there are total 8 queues
415       Each bit position of this field maps to a queue. there are total 8 queues
420       Receive Store and Forward. When this field is set, DWC_xgmac reads a
422       Each bit position of this field maps to a queue. there are total 8 queues
429       Each bit position of this field maps to a queue. there are total 8 queues
434       Forward Undersized Good Packets. When this field is set, the Rx queue forwards
436       Each bit position of this field maps to a queue. there are total 8 queues
441       Priorities Mapped to Traffic Class. This field determines if the transmit
444       matching the priorities programmed in this field.
451       Transmission Selection Algorithm. This field is used to assign a transmission
469       programmed in this field in units of bytes, the MAC declares
471       this field must be greater than or equal to 1518 bytes. Any