1 /*
2  * Copyright 2023 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__
8 #define ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_QOS_H__
9 
10 #include <fsl_device_registers.h>
11 #include <zephyr/drivers/clock_control.h>
12 
13 /* Different platforms named the peripheral different in the register definitions */
14 #ifdef CONFIG_SOC_SERIES_MCXN
15 #undef ENET
16 #define ENET_QOS_NAME ENET
17 #define ENET_QOS_ALIGNMENT 4
18 typedef ENET_Type enet_qos_t;
19 #else
20 #error "ENET_QOS not enabled on this SOC series"
21 #endif
22 
23 #define _PREFIX_UNDERLINE(x) _##x
24 #define _ENET_QOS_REG_FIELD(reg, field) MACRO_MAP_CAT(_PREFIX_UNDERLINE, reg, field, MASK)
25 #define _ENET_QOS_REG_MASK(reg, field) CONCAT(ENET_QOS_NAME, _ENET_QOS_REG_FIELD(reg, field))
26 
27 /* Deciphers value of a field from a read value of an enet qos register
28  *
29  * reg: name of the register
30  * field: name of the bit field within the register
31  * val: value that had been read from the register
32  */
33 #define ENET_QOS_REG_GET(reg, field, val) FIELD_GET(_ENET_QOS_REG_MASK(reg, field), val)
34 
35 /* Prepares value of a field for a write to an enet qos register
36  *
37  * reg: name of the register
38  * field: name of the bit field within the register
39  * val: value to put into the field
40  */
41 #define ENET_QOS_REG_PREP(reg, field, val) FIELD_PREP(_ENET_QOS_REG_MASK(reg, field), val)
42 
43 
44 #define ENET_QOS_ALIGN_ADDR_SHIFT(x) (x >> (ENET_QOS_ALIGNMENT >> 1))
45 
46 struct nxp_enet_qos_config {
47 	const struct pinctrl_dev_config *pincfg;
48 	const struct device *clock_dev;
49 	clock_control_subsys_t clock_subsys;
50 	enet_qos_t *base;
51 };
52 #define ENET_QOS_MODULE_CFG(module_dev) ((struct nxp_enet_qos_config *) module_dev->config)
53 
54 #endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_NXP_ENET_H__ */
55