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/Zephyr-latest/dts/bindings/pinctrl/
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
32 /* Configure GPIO to push-pull mode */
33 drive-push-pull;
35 output-high;
[all …]
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
31 bias-pull-up:
33 description: enable pull-up resistor
35 bias-pull-down:
37 description: enable pull-down resistor
[all …]
Dti,cc13xx-cc26xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
29 - drive-strength: Minimum current that can be sourced from the pin.
30 - input-enable: enable input.
31 - input-schmitt-enable: enable input schmitt circuit.
32 - ti,input-edge-detect: enable and configure edge detection interrupts
[all …]
Dinfineon,cat1-pinctrl.yaml4 # SPDX-License-Identifier: Apache-2.0
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
30 * input-enable (input-buffer)
[all …]
Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
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Despressif,esp32-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 states are composed by groups of pre-defined pin muxing definitions and user
10 Each Zephyr-based application has its own set of pin muxing/pin configuration
11 requirements. The next steps use ESP-WROVER-KIT's I2C_0 to illustrate how one
15 Suppose an application running on top of the ESP-WROVER-KIT board, for some
17 that board's original device tree source file (i.e., 'esp_wrover_kit.dts'),
18 you'll notice that the I2C_0 node is already assigned to a pre-defined state.
22 #include "esp_wrover_kit-pinctrl.dtsi"
26 pinctrl-0 = <&i2c0_default>;
27 pinctrl-names = "default";
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/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-nrf-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nRF-specific GPIO Flags
11 * @defgroup gpio_interface_nrf nRF-specific GPIO Flags
17 * @name nRF GPIO drive flags
18 * @brief nRF GPIO drive flags
20 * Standard (S) or High (H) drive modes can be applied to both pin levels, 0 or
21 * 1. High drive mode will increase current capabilities of the pin (refer to
24 * When the pin is configured to operate in open-drain mode (wired-and), the
25 * drive mode can only be selected for the 0 level (1 is disconnected).
26 * Similarly, when the pin is configured to operate in open-source mode
[all …]
Dgpio.h5 * SPDX-License-Identifier: Apache-2.0
33 * @name GPIO pin drive flags
39 /* Configures GPIO output in single-ended mode (open drain or open source). */
41 /* Configures GPIO output in push-pull mode */
44 /* Indicates single ended open drain mode (wired AND). */
46 /* Indicates single ended open source mode (wired OR). */
51 /** Configures GPIO output in open drain mode (wired AND).
53 * @note 'Open Drain' mode also known as 'Open Collector' is an output
58 /** Configures GPIO output in open source mode (wired OR).
60 * @note 'Open Source' is a term used by software engineers to describe output
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/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi2 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
16 bias-disable;
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 drive-strength = "r0-6";
27 slew-rate = "fast";
28 nxp,speed = "50-mhz";
29 bias-pull-down-value = "100k";
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/Zephyr-latest/subsys/usb/usb_c/
Dusbc_tc_src_states.c4 * SPDX-License-Identifier: Apache-2.0
21 * 1: The port shall not drive VBUS or VCONN.
38 const struct device *dev = tc->dev; in tc_unattached_src_run()
47 if (tcpc_is_cc_at_least_one_rd(tc->cc1, tc->cc2)) { in tc_unattached_src_run()
74 const struct device *dev = tc->dev; in tc_unattached_wait_src_entry()
75 struct usbc_port_data *data = dev->data; in tc_unattached_wait_src_entry()
76 const struct device *tcpc = data->tcpc; in tc_unattached_wait_src_entry()
84 usbc_timer_start(&tc->tc_t_vconn_off); in tc_unattached_wait_src_entry()
90 const struct device *dev = tc->dev; in tc_unattached_wait_src_run()
93 if (usbc_timer_expired(&tc->tc_t_vconn_off)) { in tc_unattached_wait_src_run()
[all …]
/Zephyr-latest/drivers/input/
Dinput_npcx_kbd.c5 * SPDX-License-Identifier: Apache-2.0
34 /* Keyboard scan input (KSI) wake-up irq */
36 /* Size of keyboard inputs-wui mapping array */
59 const struct npcx_kbd_config *const config = dev->config; in npcx_kbd_set_detect_mode()
60 const struct input_kbd_matrix_common_config *common = &config->common; in npcx_kbd_set_detect_mode()
63 for (int i = 0; i < common->row_size; i++) { in npcx_kbd_set_detect_mode()
64 npcx_miwu_irq_get_and_clear_pending(&config->wui_maps[i]); in npcx_kbd_set_detect_mode()
67 irq_enable(config->irq); in npcx_kbd_set_detect_mode()
69 irq_disable(config->irq); in npcx_kbd_set_detect_mode()
75 const struct npcx_kbd_config *config = dev->config; in npcx_kbd_drive_column()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_npm6001.c3 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nordic-npm6001-gpio.h>
47 const struct gpio_npm6001_config *config = dev->config; in gpio_npm6001_port_get_raw()
53 return -EWOULDBLOCK; in gpio_npm6001_port_get_raw()
56 ret = i2c_write_read_dt(&config->bus, &reg, sizeof(reg), &val, in gpio_npm6001_port_get_raw()
70 const struct gpio_npm6001_config *config = dev->config; in gpio_npm6001_port_set_bits_raw()
74 return -EWOULDBLOCK; in gpio_npm6001_port_set_bits_raw()
77 return i2c_write_dt(&config->bus, buf, sizeof(buf)); in gpio_npm6001_port_set_bits_raw()
83 const struct gpio_npm6001_config *config = dev->config; in gpio_npm6001_port_clear_bits_raw()
87 return -EWOULDBLOCK; in gpio_npm6001_port_clear_bits_raw()
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Dgpio_npcx.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/gpio/nuvoton-npcx-gpio.h>
50 ((struct gpio_reg *)((const struct gpio_npcx_config *)(dev)->config)->base)
64 const struct gpio_npcx_config *const config = dev->config; in npcx_gpio_enable_io_pads()
65 const struct npcx_wui *io_wui = &config->wui_maps[pin]; in npcx_gpio_enable_io_pads()
67 if (io_wui->table == NPCX_MIWU_TABLE_NONE) { in npcx_gpio_enable_io_pads()
68 LOG_ERR("Cannot enable GPIO(%x, %d) pad", config->port, pin); in npcx_gpio_enable_io_pads()
73 * If this pin is configured as a GPIO interrupt source, do not in npcx_gpio_enable_io_pads()
83 const struct gpio_npcx_config *const config = dev->config; in npcx_gpio_disable_io_pads()
84 const struct npcx_wui *io_wui = &config->wui_maps[pin]; in npcx_gpio_disable_io_pads()
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Dgpio_b91.c4 * SPDX-License-Identifier: Apache-2.0
21 ((const struct gpio_b91_config *)dev->config)->gpio_base)
24 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
27 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
29 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
30 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
49 /* Pull-up/down resistors */
73 uint8_t ds; /* DS: drive strength. 1: maximum (default), 0: minimal */
102 BM_SET(gpio->irq_en, BIT(pin)); in gpiob_b91_irq_en_set()
119 BM_CLR(gpio->irq_en, BIT(pin)); in gpiob_b91_irq_en_clr()
[all …]
Dgpio_mchp_xec_v2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
52 /* Each GPIO pin 32-bit control register located consecutively in memory */
55 const struct gpio_xec_config *config = dev->config; in pin_ctrl_addr()
57 return config->pcr1_base + ((uintptr_t)pin * 4u); in pin_ctrl_addr()
60 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
63 const struct gpio_xec_config *config = dev->config; in pin_parin_addr()
65 return config->parin_addr; in pin_parin_addr()
68 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
3 * Copyright (c) 2020-2022 Gerson Fernando Budke
4 * SPDX-License-Identifier: Apache-2.0
27 /* Open-Drain is a reserved entry at pinctrl driver */
29 /* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
32 /* Output-Enable, see dts/pinctrl/pincfg-node.yaml */
35 /* Drive-Strength, 0mA means normal, any other value means stronger */
97 * - configure pin(s) as input.
98 * - connect pin(s) to a peripheral B and enable pull-up.
108 * operating in any Sleep mode where its source clock is running.
/Zephyr-latest/boards/st/stm32g081b_eval/
Dstm32g081b_eval.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/g0/stm32g081rbtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 compatible = "st,stm32g081-eval";
18 zephyr,shell-uart = &usart3;
24 compatible = "gpio-leds";
44 compatible = "gpio-keys";
83 volt-sensor0 = &vref;
84 volt-sensor1 = &vbat;
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/Zephyr-latest/boards/adi/max32690fthr/doc/
Dindex.rst7 implement ultra low-power wireless solutions using MAX32690 Arm© Cortex®-M4F
10 dual-row header footprint that is compatible with Adafruit Feather Wing
16 - MAX32690 MCU:
18 - Ultra-Efficient Microcontroller for Battery-Powered Applications
20 - 120MHz Arm Cortex-M4 Processor with FPU
21 - 7.3728MHz and 60MHz Low-Power Oscillators
22 - External Crystal Support (32MHz required for BLE)
23 - 32.768kHz RTC Clock (Requires External Crystal)
24 - 8kHz Always-On Ultra-Low Power Oscillator
25 - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON)
[all …]
/Zephyr-latest/doc/releases/
Dmigration-guide-4.1.rst25 perform a full erase, pass the ``--erase`` option when executing ``west flash``.
35 compiler option ``-fstack-protector-all``. Users who wish to use this option must now enable
52 array property ``input-codes``.
54 If the devicetree property ``int-gpios`` is present, interrupt mode is used
57 the devicetree property ``poll-interval-ms``.
68 * MCO clock source and prescaler are now exclusively configured by the DTS
78 * If a platform has a CSPRNG source available (i.e. :kconfig:option:`CONFIG_CSPRNG_ENABLED`
80 is the default choice for random number source instead of
84 * The newly-added Kconfig option :kconfig:option:`CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT`
92 Trusted Firmware-M
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/Zephyr-latest/boards/arm/v2m_musca_b1/doc/
Dindex.rst10 on the V2M Musca B1 board. It provides support for the Musca B1 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
31 - ARM Cortex-M33
32 - ARM IoT Subsystem for Cortex-M33
33 - Memory
35 - 512KB on-chip system memory SRAM.
36 - 8MB of external QSPI flash.
[all …]
/Zephyr-latest/doc/project/
Ddev_env_and_tools.rst1 .. _dev-environment-and-tools:
13 GitHub is used to support the standard open source practice of submitting
42 code-owner review. Additionally, some changes might require further discussions
50 :figclass: align-center
55 ---------
57 - An author of a change can suggest in his pull-request which category a change
61 - The project will use the label system to categorize the pull requests.
62 - Changes should not be merged before the minimal time has expired.
65 -----------------
82 Trivial changes are those that appear obvious enough and do not require maintainer or code-owner
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/Zephyr-latest/boards/adi/max32690evkit/doc/
Dindex.rst6 of the MAX32690 microcontroller, which is an advanced system-on-chip (SoC).
7 It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and
25 - MAX32690 MCU:
27 - Ultra-Efficient Microcontroller for Battery-Powered Applications
29 - 120MHz Arm Cortex-M4 Processor with FPU
30 - 7.3728MHz and 60MHz Low-Power Oscillators
31 - External Crystal Support (32MHz required for BLE)
32 - 32.768kHz RTC Clock (Requires External Crystal)
33 - 8kHz Always-On Ultra-Low Power Oscillator
34 - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON)
[all …]
/Zephyr-latest/boards/arm/v2m_musca_s1/doc/
Dindex.rst3 ARM V2M Musca-S1
10 on the V2M Musca-S1 board. It provides support for the Musca-S1 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
20 :alt: ARM V2M Musca-S1
22 More information about the board can be found at the `V2M Musca-S1 Website`_.
27 ARM V2M MUSCA-S1 provides the following hardware components:
29 - ARM Cortex-M33 (with FPU and DSP)
[all …]
/Zephyr-latest/boards/adi/apard32690/doc/
Dindex.rst5 The AD-APARD32690-SL is a platform for prototyping intelligent, secure, and connected field devices.
6 It has an Arduino Mega-compatible form factor and two Pmod-compatible connectors.
7 The system includes the MAX32690 ARM Cortex-M4 with FPU-Based Microcontroller and Bluetooth LE 5.2.
10 security features such as for root-of-trust, mutual authentication, data confidentiality and
12 A 10 Mbps single-pair Ethernet link using the ADIN1110 10BASE-T1L MAC/PHY, enables remote
13 data acquisition and system configuration. The 10BASE-T1L interface also supports Single-pair
22 - MAX32690 MCU:
24 - Ultra-Efficient Microcontroller for Battery-Powered Applications
26 - 120MHz Arm Cortex-M4 Processor with FPU
27 - 7.3728MHz and 60MHz Low-Power Oscillators
[all …]
/Zephyr-latest/boards/olimex/stm32_e407/doc/
Dindex.rst6 The OLIMEX-STM32-E407 board is open source hardware and is based on
7 the STMicroelectronics STM32F407ZG ARM Cortex-M4 CPU.
13 `OLIMEX-STM32-E407 website`_ and `OLIMEX-STM32-E407 user manual`_.
23 +------------+------------+----------------------+
26 | NVIC | on-chip | nested vectored |
28 +------------+------------+----------------------+
29 | SYSTICK | on-chip | system clock |
30 +------------+------------+----------------------+
31 | UART | on-chip | serial port |
32 +------------+------------+----------------------+
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