1.. zephyr:board:: max32690evkit 2 3Overview 4******** 5The MAX32690 evaluation kit (EV kit) provides a platform for evaluating the capabilities 6of the MAX32690 microcontroller, which is an advanced system-on-chip (SoC). 7It features an Arm® Cortex®-M4F CPU for efficient computation of complex functions and 8algorithms, and the latest generation Bluetooth® 5 Low Energy (Bluetooth LE) radio designed 9for wearable and hearable fitness devices, portable and wearable wireless medical devices, 10industrial sensors/networks, internet of things (IoT), and asset tracking. 11 12The Zephyr port is running on the MAX32690 MCU. 13 14.. image:: img/max32690evkit.jpg 15 :align: center 16 :alt: MAX32690 EVKIT Front 17 18.. image:: img/max32690evkit_img2.jpg 19 :align: center 20 :alt: MAX32690 Back 21 22Hardware 23******** 24 25- MAX32690 MCU: 26 27 - Ultra-Efficient Microcontroller for Battery-Powered Applications 28 29 - 120MHz Arm Cortex-M4 Processor with FPU 30 - 7.3728MHz and 60MHz Low-Power Oscillators 31 - External Crystal Support (32MHz required for BLE) 32 - 32.768kHz RTC Clock (Requires External Crystal) 33 - 8kHz Always-On Ultra-Low Power Oscillator 34 - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON) 35 - TBDμW/MHz Executing from Cache at 1.1V 36 - 1.8V and 3.3V I/O with No Level Translators 37 - External Flash & SRAM Expansion Interfaces 38 39 - Bluetooth 5.2 LE Radio 40 41 - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing 42 - Fully Open-Source Bluetooth 5.2 Stack Available 43 - Supports AoA, AoD, LE Audio, and Mesh 44 - High-Throughput (2Mbps) Mode 45 - Long-Range (125kbps and 500kbps) Modes 46 - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm 47 - Single-Ended Antenna Connection (50Ω) 48 49 - Multiple Peripherals for System Control 50 51 - 16-Channel DMA 52 - Up To Five Quad SPI Master (60MHz)/Slave (48MHz) 53 - Up To Four 1Mbaud UARTs with Flow Control 54 - Up To Two 1MHz I2C Master/Slave 55 - I2S Master/Slave 56 - Eight External Channel, 12-bit 1MSPS SAR ADC w/ on-die temperature sensor 57 - USB 2.0 Hi-Speed Device 58 - 16 Pulse Train Engines 59 - Up To Six 32-Bit Timers with 8mA High Drive 60 - Up To Two CAN 2.0 Controllers 61 - Up To Four Micro-Power Comparators 62 - 1-Wire Master 63 64 - Security and Integrity 65 66 - ChipDNA Physically Un-clonable Function (PUF) 67 - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG) 68 - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256 69 - Secure Boot ROM 70 71- External devices connected to the MAX32690EVKIT: 72 73 - Bluetooth SMA Connector with a Hinged 2.4GHz Whip Antenna 74 - 3-Pin Terminal Block for CAN Bus 2.0 75 - Selectable On-Board High-Precision Voltage Reference 76 - On-Board HyperRAM 77 - Stereo Audio Codec with Line-In and Line-Out 3.5mm Jacks 78 - 128 x 128 (1.45in) Color TFT Display 79 - USB 2.0 Micro-B Interface to the MAX32690 80 - USB 2.0 Micro-B to Serial UART 81 - Board Power Provided by either USB Port 82 - Jumpers to Enable Optional Pull-Up Resistors on I2C port 83 - All GPIOs Signals Accessed through 0.1in Headers 84 - Three Analog Inputs Accessed through 0.1in Headers with Optional Filtering 85 - SWD 10-Pin Header 86 - On-Board 3.3V, 1.8V, and 1.1V LDO Regulators 87 - Individual Power Measurement on All IC Rails through Jumpers 88 - Two General-Purpose LEDs and One GeneralPurpose Push Button Switch 89 90 91Supported Features 92================== 93 94Below interfaces are supported by Zephyr on MAX32690EVKIT. 95 96+-----------+------------+-------------------------------------+ 97| Interface | Controller | Driver/Component | 98+===========+============+=====================================+ 99| NVIC | on-chip | nested vector interrupt controller | 100+-----------+------------+-------------------------------------+ 101| SYSTICK | on-chip | systick | 102+-----------+------------+-------------------------------------+ 103| CLOCK | on-chip | clock and reset control | 104+-----------+------------+-------------------------------------+ 105| GPIO | on-chip | gpio | 106+-----------+------------+-------------------------------------+ 107| UART | on-chip | serial | 108+-----------+------------+-------------------------------------+ 109| SPI | on-chip | spi | 110+-----------+------------+-------------------------------------+ 111| I2C | on-chip | i2c | 112+-----------+------------+-------------------------------------+ 113| TRNG | on-chip | entropy | 114+-----------+------------+-------------------------------------+ 115| DMA | on-chip | dma controller | 116+-----------+------------+-------------------------------------+ 117| Watchdog | on-chip | watchdog | 118+-----------+------------+-------------------------------------+ 119| ADC | on-chip | adc | 120+-----------+------------+-------------------------------------+ 121| Timer | on-chip | counter | 122+-----------+------------+-------------------------------------+ 123| PWM | on-chip | pwm | 124+-----------+------------+-------------------------------------+ 125| W1 | on-chip | one wire master | 126+-----------+------------+-------------------------------------+ 127| Flash | on-chip | flash | 128+-----------+------------+-------------------------------------+ 129 130 131Connections and IOs 132=================== 133 134+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 135| Name | Name | Settings | Description | 136+===========+===============+===============+==================================================================================================+ 137| JP1 | VREF | | | 138| | | +-----------+ | +-------------------------------------------------------------------------------+ | 139| | | | 1-2 | | | Connects external voltage reference to VREF pin, must be enabled in software. | | 140| | | +-----------+ | +-------------------------------------------------------------------------------+ | 141| | | | Open | | | Disconnects external voltage reference. | | 142| | | +-----------+ | +-------------------------------------------------------------------------------+ | 143| | | | | 144+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 145| JP2 | I2C0 PU | +-----------+ | +-------------------------------------------------------------------------------+ | 146| | | | 2-1 | | | Connects VDDIO (1V8) to I2C0 pull-up resistors. | | 147| | | +-----------+ | +-------------------------------------------------------------------------------+ | 148| | | | 2-3 | | | Connects VDDIOH (3V3) to I2C0 pull-up resistors. | | 149| | | +-----------+ | +-------------------------------------------------------------------------------+ | 150| | | | Open | | | Disconnects power from I2C0 pull-up resistors. | | 151| | | +-----------+ | +-------------------------------------------------------------------------------+ | 152| | | | | 153+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 154| JP3 | I2C0_SDA_PU | +-----------+ | +-------------------------------------------------------------------------------+ | 155| | | | 1-2 | | | Connects pull-up to I2C0A_SDA (P2.7) sourced by I2C0 PU (JP2). | | 156| | | +-----------+ | +-------------------------------------------------------------------------------+ | 157| | | | Open | | | Disconnects pull-up from I2C0A_SDA (P2.7) sourced by I2C0 PU (JP2). | | 158| | | +-----------+ | +-------------------------------------------------------------------------------+ | 159| | | | | 160+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 161| JP4 | I2C0_SCL_PU | +-----------+ | +-------------------------------------------------------------------------------+ | 162| | | | 1-2 | | | Connects pull-up to I2C0A_SCL (P2.8) sourced by I2C0 PU (JP2). | | 163| | | +-----------+ | +-------------------------------------------------------------------------------+ | 164| | | | Open | | | Disconnects pull-up from I2C0A_SCL (P2.8) sourced by I2C0 PU (JP2). | | 165| | | +-----------+ | +-------------------------------------------------------------------------------+ | 166| | | | | 167+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 168| JP5 | LED0 EN | +-----------+ | +-------------------------------------------------------------------------------+ | 169| | | | 1-2 | | | Connects red LED D1 to P0.14. | | 170| | | +-----------+ | +-------------------------------------------------------------------------------+ | 171| | | | Open | | | Disconnects red LED D1 from P0.14. | | 172| | | +-----------+ | +-------------------------------------------------------------------------------+ | 173| | | | | 174+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 175| JP6 | LED1 EN | +-----------+ | +-------------------------------------------------------------------------------+ | 176| | | | 1-2 | | | Connects green LED D2 to P2.12. | | 177| | | +-----------+ | +-------------------------------------------------------------------------------+ | 178| | | | Open | | | Disconnects green LED D2 from P2.12. | | 179| | | +-----------+ | +-------------------------------------------------------------------------------+ | 180| | | | | 181+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 182| JP7 | RX EN | +-----------+ | +-------------------------------------------------------------------------------+ | 183| | | | 1-2 | | | Connects the USB - serial bridge to UART2A_RX (P1.9). | | 184| | | +-----------+ | +-------------------------------------------------------------------------------+ | 185| | | | Open | | | Disconnects the USB - serial bridge from UART2A_RX (P1.9). | | 186| | | +-----------+ | +-------------------------------------------------------------------------------+ | 187| | | | | 188+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 189| JP8 | TX EN | +-----------+ | +-------------------------------------------------------------------------------+ | 190| | | | 1-2 | | | Connects the USB - serial bridge to UART2A_TX (P1.10). | | 191| | | +-----------+ | +-------------------------------------------------------------------------------+ | 192| | | | Open | | | Disconnects the USB - serial bridge from UART2A_TX (P1.10). | | 193| | | +-----------+ | +-------------------------------------------------------------------------------+ | 194| | | | | 195+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 196| JP9 | P1_7 SEL | +-----------+ | +-------------------------------------------------------------------------------+ | 197| | | | 2-1 | | | Connects the USB - serial bridge to UART2A_CTS (P1.7). | | 198| | | +-----------+ | +-------------------------------------------------------------------------------+ | 199| | | | 2-3 | | | Connects I2C2C_SDA (P1.7) to the codec. | | 200| | | +-----------+ | +-------------------------------------------------------------------------------+ | 201| | | | | 202+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 203| JP10 | P1_8 SEL | +-----------+ | +-------------------------------------------------------------------------------+ | 204| | | | 2-1 | | | Connects the USB - serial bridge to UART2A_RTS (P1.8). | | 205| | | +-----------+ | +-------------------------------------------------------------------------------+ | 206| | | | 2-3 | | | Connects I2C2C_SCL (P1.8) to the codec. | | 207| | | +-----------+ | +-------------------------------------------------------------------------------+ | 208| | | | | 209+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 210| JP11 | V_AUX SEL | +-----------+ | +-------------------------------------------------------------------------------+ | 211| | | | 2-1 | | | Connects V_AUX to 1V8. | | 212| | | +-----------+ | +-------------------------------------------------------------------------------+ | 213| | | | 2-3 | | | Connects V_AUX to 3V3. | | 214| | | +-----------+ | +-------------------------------------------------------------------------------+ | 215| | | | | 216+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 217| JP12 | VDD3A EN | +-----------+ | +-------------------------------------------------------------------------------+ | 218| | | | 1-2 | | | Connects 3V3 to VDD3A. | | 219| | | +-----------+ | +-------------------------------------------------------------------------------+ | 220| | | | Open | | | Disconnects 3V3 from VDD3A. | | 221| | | +-----------+ | +-------------------------------------------------------------------------------+ | 222| | | | | 223+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 224| JP13 | VDDIOH EN | +-----------+ | +-------------------------------------------------------------------------------+ | 225| | | | 1-2 | | | Connects 3V3 to VDDIOH. | | 226| | | +-----------+ | +-------------------------------------------------------------------------------+ | 227| | | | Open | | | Disconnects 3V3 from VDDIOH. | | 228| | | +-----------+ | +-------------------------------------------------------------------------------+ | 229| | | | | 230+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 231| JP14 | VDDB EN | +-----------+ | +-------------------------------------------------------------------------------+ | 232| | | | 1-2 | | | Connects a 3V3 LDO sourced by USB_VBUS (CN1) to VDDB. | | 233| | | +-----------+ | +-------------------------------------------------------------------------------+ | 234| | | | Open | | | Disconnects a 3V3 LDO sourced by USB_VBUS (CN1) from VDDB. | | 235| | | +-----------+ | +-------------------------------------------------------------------------------+ | 236| | | | | 237+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 238| JP15 | VDDA EN | +-----------+ | +-------------------------------------------------------------------------------+ | 239| | | | 1-2 | | | Connects 1V8 to VDDA. | | 240| | | +-----------+ | +-------------------------------------------------------------------------------+ | 241| | | | Open | | | Disconnects 1V8 from VDDA. | | 242| | | +-----------+ | +-------------------------------------------------------------------------------+ | 243| | | | | 244+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 245| JP16 | VDDIO EN | +-----------+ | +-------------------------------------------------------------------------------+ | 246| | | | 1-2 | | | Connects 1V8 to VDDIO. | | 247| | | +-----------+ | +-------------------------------------------------------------------------------+ | 248| | | | Open | | | Disconnects 1V8 from VDDIO. | | 249| | | +-----------+ | +-------------------------------------------------------------------------------+ | 250| | | | | 251+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 252| JP17 | VCORE EN | +-----------+ | +-------------------------------------------------------------------------------+ | 253| | | | 1-2 | | | Connects 1V1 to VCORE. | | 254| | | +-----------+ | +-------------------------------------------------------------------------------+ | 255| | | | Open | | | Disconnects 1V1 from VCORE. | | 256| | | +-----------+ | +-------------------------------------------------------------------------------+ | 257| | | | | 258+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 259| JP18 | BLE LDO EN | +-----------+ | +-------------------------------------------------------------------------------+ | 260| | | | 1-2 | | | Connects 1V4 to BLE_LDO. | | 261| | | +-----------+ | +-------------------------------------------------------------------------------+ | 262| | | | Open | | | Disconnects 1V4 from BLE_LDO. | | 263| | | +-----------+ | +-------------------------------------------------------------------------------+ | 264| | | | | 265+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 266| JH6 | ANALOG PORT3 | +-----------+ | +-------------------------------------------------------------------------------+ | 267| | | | 1-2 | | | Connects LPUART0B_RX (P3.0) to the SWD connector. | | 268| | | +-----------+ | +-------------------------------------------------------------------------------+ | 269| | | | 3-4 | | | Connects LPUART0B_TX (P3.1) to the SWD connector. | | 270| | | +-----------+ | +-------------------------------------------------------------------------------+ | 271| | | | Open | | | Disconnects LPUART0B_RX (P3.0) and LPUART0B_TX (P3.1) from the SWD connector. | | 272| | | +-----------+ | +-------------------------------------------------------------------------------+ | 273| | | | | 274+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 275 276Programming and Debugging 277************************* 278 279Flashing 280======== 281 282The MAX32690 MCU can be flashed by connecting an external debug probe to the 283SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3. 284Logic levels are fixed to VDDIO (1.8V). 285 286Once the debug probe is connected to your host computer, then you can simply run the 287``west flash`` command to write a firmware image into flash. 288 289.. note:: 290 291 This board uses OpenOCD as the default debug interface. You can also use 292 a Segger J-Link with Segger's native tooling by overriding the runner, 293 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should 294 be connected to the standard 2*5 pin debug connector (JW3) using an 295 appropriate adapter board and cable. 296 297Debugging 298========= 299 300Please refer to the `Flashing`_ section and run the ``west debug`` command 301instead of ``west flash``. 302 303References 304********** 305 306- `MAX32690EVKIT web page`_ 307 308.. _MAX32690EVKIT web page: 309 https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32690EVKIT.html 310
