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/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_cavs.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 lpgpdma0: dma@7c000 {
12 compatible = "intel,adsp-gpdma";
13 #dma-cells = <1>;
17 interrupt-parent = <&cavs_intc3>;
18 dma-buf-size-alignment = <4>;
19 dma-copy-alignment = <4>;
24 lpgpdma1: dma@7d000 {
25 compatible = "intel,adsp-gpdma";
26 #dma-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/dma/
Dmicrochip,xec-dmac.yaml1 description: Microchip XEC DMA controller
3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
24 aggregated-girq:
27 If DMA driver uses aggregated interrupt mode
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
50 # Example of devicetree dma channel configuration:
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Dnxp,lpc-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP LPC DMA controller
6 compatible: "nxp,lpc-dma"
8 include: dma-controller.yaml
17 dma-channels:
20 nxp,dma-num-of-otrigs:
22 description: Number of Inputmux connections a DMA channel can receive from
24 nxp,dma-otrig-base-address:
26 description: Address used when listening to Inputmux DMA signals
28 nxp,dma-itrig-base-address:
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Drenesas,smartbond-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 include: dma-controller.yaml
6 description: Renesas Smartbond(tm) DMA
8 compatible: "renesas,smartbond-dma"
17 block-count:
23 "#dma-cells":
26 # - #dma-cells : Must be <2>.
27 # channel: dma channel to be reserved
28 # config: peripheral's dma request line. Valid values are defined in dt-bindings/dma/dma_smartbond.h
30 dma-cells:
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Darm,dma-pl330.yaml2 # SPDX-License-Identifier: Apache-2.0
5 PL330 DMA Controller
7 A phandle to the DMA controller plus "channel" integer cell specifying
10 Example for pl330 DMA Controller
12 compatible = "arm,dma-pl330";
14 dma-channels = <8>;
15 #dma-cells = <1>;
18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
20 compatible = "brcm,iproc-pcie-ep";
23 dma-names = "txdma", "rxdma";
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Dsnps,designware-dma-axi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Synopsys Designware axi DMA Controller node
6 compatible: "snps,designware-dma-axi"
8 include: [dma-controller.yaml, reset-device.yaml]
14 dma-channels:
20 "#dma-cells":
23 # #dma-cells : Must be <1>.
25 # Example of device-tree dma channel configuration:
28 # /* Configure DMA */
30 # dma-names = "tx", "rx";
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Dinfineon,xmc4xxx-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 XMC4xxx DMA Controller
7 compatible: "infineon,xmc4xxx-dma"
9 include: dma-controller.yaml
18 dma-channels:
20 description: Number of DMA channels supported by the controller
22 "#dma-cells":
25 dma-cells:
26 - channel
27 - priority
[all …]
Dintel,adsp-hda.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for Intel ADSP HDA DMA controllers
6 include: dma-controller.yaml
12 dma-channels:
15 "#dma-cells":
18 "dma-buf-addr-alignment":
21 "dma-buf-size-alignment":
24 "dma-copy-alignment":
27 dma-cells:
28 - channel
Datmel,sam0-dmac.yaml1 description: Atmel SAM0 DMA controller
3 compatible: "atmel,sam0-dmac"
5 include: dma-controller.yaml
14 "#dma-cells":
17 # #dma-cells : Must be <2>.
26 # Example of devicetree dma channel configuration:
29 # /* Configure DMA channels for async operation */
31 # dma-names = "rx", "tx";
37 dma-cells:
38 - channel
[all …]
Dadi,max32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32 DMA
6 compatible: "adi,max32-dma"
8 include: dma-controller.yaml
14 "#dma-cells":
18 dma-cells:
19 - channel
20 - slot
Dsilabs,si32-dma.yaml3 # SPDX-License-Identifier: Apache-2.0
5 description: Si32 DMA controller
7 compatible: "silabs,si32-dma"
9 include: dma-controller.yaml
18 dma-channels:
23 "#dma-cells":
26 dma-cells:
27 - channel
28 - high-prio
29 - rpower
Dsnps,designware-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Synopsys Designware DMA Controller node
6 compatible: "snps,designware-dma"
8 include: dma-controller.yaml
17 "#dma-cells":
20 dma-cells:
21 - channel
Dinfineon,cat1-dma.yaml4 # SPDX-License-Identifier: Apache-2.0
6 description: Infineon CAT1 DMA node
8 compatible: "infineon,cat1-dma"
10 include: dma-controller.yaml
19 "#dma-cells":
22 dma-cells:
23 - channel
Drenesas,rz-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 RZ DMA controller
9 config: A 32bit mask specifying the DMA channel configuration
17 dma-names = "rx", "tx";
20 compatible: "renesas,rz-dma"
22 include: [dma-controller.yaml, pinctrl-device.yaml]
31 dma-channels:
34 "#dma-cells":
37 dma-cells:
38 - channel
[all …]
Dintel,lpss.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: LPSS DMA Controller node
8 include: dma-controller.yaml
11 "#dma-cells":
14 dma-cells:
15 - channel
Draspberrypi,pico-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Raspberry Pi Pico DMA
10 Use the definitions defined in `zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h`,
11 or `zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h`
13 channel-config: A 32bit mask specifying the DMA channel configuration
14 - bit 3: Enable Quiet IRQ
15 - bit 1: Enable Byte Swap
16 - bit 0: Enable High Priority
18 compatible: "raspberrypi,pico-dma"
20 include: [dma-controller.yaml, reset-device.yaml]
[all …]
Dwch,wch-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 WCH DMA controller
7 The WCH DMA controller is a general-purpose direct memory access controller
9 Every channel is capable of memory-to-memory, memory-to-peripheral, and
10 peripheral-to-memory access.
12 Mapping of peripheral requests to DMA channels is limited and SoC specific.
13 Commonly, each peripheral request maps to just a single DMA channel.
18 compatible: "wch,wch-dma"
20 include: dma-controller.yaml
29 "#dma-cells":
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Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32U5 DMA controller.
7 It is present on stm32U5 devices as a GP DMA
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
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Dsilabs,siwx91x-dma.yaml1 description: Silabs SiWx91x DMA node
3 compatible: "silabs,siwx91x-dma"
5 include: dma-controller.yaml
11 silabs,sram-desc-addr:
21 "#dma-cells":
25 dma-cells:
26 - channel
Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
29 Andes DMA controller
30 channel: a phandle to the DMA controller plus the following four integer cells:
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/Zephyr-latest/dts/arm/silabs/
Dsim3u.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <dt-bindings/gpio/gpio.h>
13 zephyr,flash-controller = &flash;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m3";
23 clock-frequency = <20000000>;
29 compatible = "mmio-sram";
33 compatible = "silabs,si32-pinctrl";
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/Zephyr-latest/dts/bindings/test/
Dvnd,dma.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: VND DMA controller
6 compatible: "vnd,dma"
8 include: dma-controller.yaml
17 "#dma-cells":
20 dma-cells:
21 - channel
22 - slot
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S3x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/st/u0/
Dstm32u073.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32u073", "st,stm32u0", "simple-bus";
14 compatible = "st,stm32-i2c-v2";
15 clock-frequency = <I2C_BITRATE_STANDARD>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 interrupt-names = "combined";
26 compatible = "st,stm32-lptim";
28 #address-cells = <1>;
29 #size-cells = <0>;
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/Zephyr-latest/dts/common/broadcom/
Dviper-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 clock-frequency = <25000000>;
18 reg-shift = <2>;
25 clock-frequency = <100000000>;
26 reg-shift = <2>;
31 compatible = "arm,dma-pl330";
34 reg-names = "pl330_regs",
37 dma-channels = <8>;
38 #dma-cells = <1>;
43 #address-cells = <2>;
[all …]

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