1# Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com> 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 WCH DMA controller 6 7 The WCH DMA controller is a general-purpose direct memory access controller 8 featuring between 7 and 11 independent channels. 9 Every channel is capable of memory-to-memory, memory-to-peripheral, and 10 peripheral-to-memory access. 11 12 Mapping of peripheral requests to DMA channels is limited and SoC specific. 13 Commonly, each peripheral request maps to just a single DMA channel. 14 The controller supports 8, 16, and 32 bit width memory access. 15 16 It is present on WCH CH32V and CH32X series SoCs. 17 18compatible: "wch,wch-dma" 19 20include: dma-controller.yaml 21 22properties: 23 reg: 24 required: true 25 26 interrupts: 27 required: true 28 29 "#dma-cells": 30 const: 1 31 32dma-cells: 33 - channel 34
