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/Zephyr-latest/dts/bindings/mipi-dsi/
Dmipi-dsi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI-DSI devices
8 on-bus: mipi-dsi
14 data-lanes:
18 Number of data lanes.
20 pixel-format:
24 Pixel format. Available formats in dt-bindings/mipi_dsi/mipi_dsi.h.
Dmipi-dsi-host.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI-DSI hosts
8 bus: mipi-dsi
11 "#address-cells":
15 "#size-cells":
19 phy-clock:
23 least (pixel clock * bits per output pixel) / number of mipi data lanes
/Zephyr-latest/boards/shields/nxp_btb44_ov5640/
Dnxp_btb44_ov5640.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/video/video-interfaces.h>
21 reset-gpios = <&nxp_cam_connector 9 GPIO_ACTIVE_LOW>;
22 powerdown-gpios = <&nxp_cam_connector 17 GPIO_ACTIVE_HIGH>;
26 remote-endpoint-label = "mipi_csi2rx_ep_in";
27 bus-type = <VIDEO_BUS_TYPE_CSI2_DPHY>;
28 data-lanes = <1 2>;
42 remote-endpoint-label = "ov5640_ep_out";
43 data-lanes = <1 2>;
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/boards/shields/rk055hdmipi4m/
Drk055hdmipi4m.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display: enable-mipi-display {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
34 reset-gpios = <&nxp_mipi_connector 28 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/tests/drivers/build_all/video/
Dmimxrt1170_evk_mimxrt1176_cm7.overlay4 * SPDX-License-Identifier: Apache-2.0
7 * with real-world devicetree nodes, to allow these tests to run on
11 #include <zephyr/dt-bindings/video/video-interfaces.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
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/Zephyr-latest/tests/drivers/build_all/display/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
13 #include <zephyr/dt-bindings/led/led.h>
14 #include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
23 gpio-controller;
25 #gpio-cells = <0x2>;
30 compatible = "zephyr,mipi-dbi-spi";
32 dc-gpios = <&test_gpio 0 0>;
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/Zephyr-latest/dts/bindings/video/
Dvideo-interfaces.yaml2 # SPDX-License-Identifier: Apache-2.0
8 data receivers, video data processors, etc. Data interfaces on these devices are
16 scheme using '#address-cells', '#size-cells' and 'reg' properties is used.
19 specify #address-cells, #size-cells properties independently for the 'port' and
25 #address-cells = <1>;
26 #size-cells = <0>;
37 Two 'endpoint' nodes must be linked with each other via their 'remote-endpoint'
39 references are currently not possible. A 'remote-endpoint-label' string is used
40 instead to be able to specify, at least, the label of the peer remote-endpoint.
44 compatible = "zephyr,video-interfaces";
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/Zephyr-latest/boards/shields/g1120b0mipi/
Dg1120b0mipi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 en_mipi_display_g1120b0mipi: enable-mipi-display {
14 compatible = "regulator-fixed";
15 regulator-name = "en_mipi_display";
16 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
17 regulator-boot-on;
21 compatible = "zephyr,lvgl-pointer-input";
23 invert-y;
31 * Note- the actual controller present on this IC is a FT3267,
36 int-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_LOW>;
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/Zephyr-latest/boards/shields/rtkmipilcdb00000be/
Drtkmipilcdb00000be.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 compatible = "zephyr,lvgl-pointer-input";
22 gt911_rtkmipilcdb00000be: gt911-rtkmipilcdb00000be@5d {
25 irq-gpios = <&renesas_mipi_connector 17 GPIO_ACTIVE_HIGH>;
26 reset-gpios = <&renesas_mipi_connector 18 GPIO_ACTIVE_LOW>;
34 compatible = "ilitek,ili9806e-dsi";
38 data-lanes = <2>;
39 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
47 input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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/Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/
Dst_b_lcd40_dsi1_mb1166.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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Dst_b_lcd40_dsi1_mb1166_a09.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
11 compatible = "zephyr,lvgl-pointer-input";
13 invert-y;
29 reset-gpios = <&dsi_lcd_qsh_030 57 GPIO_ACTIVE_HIGH>;
30 bl-gpios = <&dsi_lcd_qsh_030 53 GPIO_ACTIVE_HIGH>;
31 data-lanes = <2>;
32 pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
41 pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
43 display-timings {
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/Zephyr-latest/drivers/mipi_dsi/
Ddsi_stm32.c7 * SPDX-License-Identifier: Apache-2.0
61 const struct mipi_dsi_stm32_config *config = dev->config; in mipi_dsi_stm32_log_config()
62 struct mipi_dsi_stm32_data *data = dev->data; in mipi_dsi_stm32_log_config() local
64 LOG_DBG("DISPLAY: pix %d kHz, lane %d kHz", data->pixel_clk_khz, data->lane_clk_khz); in mipi_dsi_stm32_log_config()
66 LOG_DBG(" AutomaticClockLaneControl 0x%x", data->hdsi.Init.AutomaticClockLaneControl); in mipi_dsi_stm32_log_config()
67 LOG_DBG(" TXEscapeCkdiv %u", data->hdsi.Init.TXEscapeCkdiv); in mipi_dsi_stm32_log_config()
68 LOG_DBG(" NumberOfLanes %u", data->hdsi.Init.NumberOfLanes); in mipi_dsi_stm32_log_config()
69 LOG_DBG(" PLLNDIV %u", data->pll_init.PLLNDIV); in mipi_dsi_stm32_log_config()
70 LOG_DBG(" PLLIDF %u", data->pll_init.PLLIDF); in mipi_dsi_stm32_log_config()
71 LOG_DBG(" PLLODF %u", data->pll_init.PLLODF); in mipi_dsi_stm32_log_config()
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/Zephyr-latest/include/zephyr/drivers/
Dmipi_dsi.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public APIs for MIPI-DSI drivers
16 * @brief MIPI-DSI driver APIs
17 * @defgroup mipi_dsi_interface MIPI-DSI driver APIs
27 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
33 /** MIPI-DSI display timings. */
54 * @name MIPI-DSI Device mode flags.
66 /** Enable hsync-end packets in vsync-pulse and v-porch area */
68 /** Disable hfront-porch area */
70 /** Disable hback-porch area */
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/Zephyr-latest/drivers/memc/
Dsifive_ddr.c2 * (C) Copyright 2020-2021 SiFive, Inc.
5 * SPDX-License-Identifier: Apache-2.0
8 * https://github.com/sifive/freedom-u540-c000-bootloader
46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i))
47 #define DDR_PHY_REG(d, i) (*(d->ddrphy + i))
124 /* return bitmask of failed lanes */ in ddr_phy_fixup()
143 struct ddr_ctrl_data *ddr_ctrl = dev->data; in ddr_init()
145 LOG_DBG("start: 0x%lx", (uintptr_t)ddr_ctrl->ddr_start); in ddr_init()
146 LOG_DBG("size: 0x%lx", ddr_ctrl->ddr_size); in ddr_init()
167 size_t end_addr_16Kblocks = ((ddr_ctrl->ddr_size >> 14) & 0x7FFFFF) - 1; in ddr_init()
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/Zephyr-latest/boards/96boards/avenger96/doc/
Dindex.rst10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
11 core. Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - PMIC: STPMIC1A
16 - RAM: 1024 Mbyte @ 533MHz
17 - Storage:
19 - eMMC: v4.51: 8 Gbyte
20 - QSPI: 2Mbyte
21 - EEPROM: 128 byte
22 - microSD Socket: UHS-1 v3.01
[all …]
/Zephyr-latest/boards/st/stm32mp157c_dk2/doc/
Dstm32mp157_dk2.rst6 The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157
7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-M4 core.
10 - Common features:
12 - STM32MP157:
14 - Arm®-based dual Cortex®-A7 32 bits
15 - Cortex®-M4 32 bits
16 - embedded SRAM (448 Kbytes) for Cortex®-M4.
18 - ST PMIC STPMIC1A
19 - 4-Gbit DDR3L, 16 bits, 533 MHz
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/Zephyr-latest/boards/toradex/verdin_imx8mm/doc/
Dindex.rst9 8M Mini SoloLite. The top-tier i.MX 8M Mini Quad features four Cortex-A53 cores as the main
10 processor cluster. The cores provide complete 64-bit Armv8-A support while maintaining seamless
11 backwards compatibility with 32-bit Armv7-A software. The main cores run at up to 1.8 GHz for
14 In addition to the main CPU complex, the i.MX 8M Mini features a Cortex-M4F processor which
17 multicore system allows for the running of additional real-time operating systems on the M4 cores
18 for time- and security-critical tasks.
20 - Board features:
22 - RAM: 1GB - 2GB (LPDDR4)
23 - Storage:
25 - 4GB - 17GB eMMC
[all …]
/Zephyr-latest/boards/st/nucleo_u5a5zj_q/doc/
Dindex.rst6 The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU,
13 - STM32U5A5ZJ microcontroller in LQFP144 package
14 - Internal SMPS to generate V core logic supply
15 - Two types of extension resources:
17 - Arduino Uno V3 connectivity
18 - ST morpho extension pin headers for full access to all STM32 I/Os
20 - On-board ST-LINK/V3E debugger/programmer
21 - Flexible board power supply:
23 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
24 - ST-Link V3E
[all …]
/Zephyr-latest/include/zephyr/usb_c/
Dtcpci.h3 * SPDX-License-Identifier: Apache-2.0
13 * This file contains register addresses, fields and masks used to retrieve specific data from
15 * Registers and fields are compliant to the Type-C Port Controller Interface
19 /** Register address - vendor id */
22 /** Register address - product id */
25 /** Register address - version of TCPC */
28 /** Register address - USB TypeC version */
30 /** Mask for major part of type-c release supported */
32 /** Macro to extract the major part of type-c release supported */
34 /** Mask for minor part of type-c release supported */
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/Zephyr-latest/boards/adi/max78002evkit/doc/
Dindex.rst10 are supported, while a pair of industry-standard QWIIC connectors supports a large and growing arra…
11 development boards. An onboard stereo audio codec offers line-level audio input and output, and tac…
12 provided by a touch-enabled 2.4in TFT display. The MAX78002 energy consumption is tracked by a powe…
14 … headers. A standard coaxial power jack serves as power input, using the included 5V, 3A wall-mount
16 bridge. A third USB connector allows access to the MAX78002 energy consumption data. Rounding out t…
17 microSD connector provides the capability for inexpensive highdensity portable data storage.
32 - MAX78002 MCU:
34 - Dual-Core, Low-Power Microcontroller
36 - Arm Cortex-M4 Processor with FPU up to 120MHz
37 - 2.5MB Flash, 64KB ROM, and 384KB SRAM
[all …]
/Zephyr-latest/drivers/video/
Dov5640.c4 * SPDX-License-Identifier: Apache-2.0
18 #include <zephyr/drivers/video-controls.h>
97 #define ABS(a, b) (a > b ? a - b : b - a)
423 return -ENOTSUP; in ov5640_read_reg()
451 return -ENOTSUP; in ov5640_read_reg()
506 const struct ov5640_config *cfg = dev->config; in ov5640_set_frmival()
507 struct ov5640_data *drv_data = dev->data; in ov5640_set_frmival()
512 desired_frmrate = DIV_ROUND_CLOSEST(frmival->denominator, frmival->numerator); in ov5640_set_frmival()
516 if (ov5640_frame_rates[i] <= drv_data->cur_mode->max_frmrate && in ov5640_set_frmival()
525 {SC_PLL_CTRL1_REG, drv_data->cur_mode->mipi_frmrate_config[ind].pllCtrl1}, in ov5640_set_frmival()
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