Lines Matching +full:data +full:- +full:lanes
6 The STM32MP157-DK2 Discovery board leverages the capacities of the STM32MP157
7 multi-core processor,composed of a dual Cortex®-A7 and a single Cortex®-M4 core.
8 Zephyr OS is ported to run on the Cortex®-M4 core.
10 - Common features:
12 - STM32MP157:
14 - Arm®-based dual Cortex®-A7 32 bits
15 - Cortex®-M4 32 bits
16 - embedded SRAM (448 Kbytes) for Cortex®-M4.
18 - ST PMIC STPMIC1A
19 - 4-Gbit DDR3L, 16 bits, 533 MHz
20 - 1-Gbps Ethernet (RGMII) compliant with IEEE-802.3ab
21 - USB OTG HS
22 - Audio CODEC, with a stereo headset jack, including analog microphone input
23 - 4 user LEDs
24 - 2 user and reset push-buttons, 1 wake-up button
25 - 5 V / 3 A USB Type-CTM power supply input (not provided)
26 - Board connectors:
28 - Ethernet RJ45
29 - 4 USB Host Type-A
30 - USB Type-C
31 - DRP MIPI DSI HDMI
32 - Stereo headset jack including analog microphone input
33 - microSD card
34 - GPIO expansion connector (Raspberry Pi® shields capability)
35 - ArduinoTM Uno V3 expansion connectors
36 - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
39 - Board-specific features:
41 - 4" TFT 480×800 pixels with LED backlight, MIPI DSI interface, and capacitive
43 - Wi-Fi® 802.11b/g/n
44 - Bluetooth® Low Energy 4.1
54 - Core:
56 - 32-bit dual-core Arm® Cortex®-A7
58 - L1 32-Kbyte I / 32-Kbyte D for each core
59 - 256-Kbyte unified level 2 cache
60 - Arm® NEON™ and Arm® TrustZone®
62 - 32-bit Arm® Cortex®-M4 with FPU/MPU
64 - Up to 209 MHz (Up to 703 CoreMark®)
66 - Memories:
68 - External DDR memory up to 1 Gbyte.
69 - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +
71 - Dual mode Quad-SPI memory interface
72 - Flexible external memory controller with up to 16-bit data bus
74 - Security/safety:
76 - Secure boot, TrustZone® peripherals with Cortex®-M4 resources isolation
79 - Clock management:
81 - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
83 - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
84 - 6 × PLLs with fractional mode
86 - General-purpose input/outputs:
88 - Up to 176 I/O ports with interrupt capability
90 - Interconnect matrix
92 - 3 DMA controllers
94 - Communication peripherals:
96 - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
97 - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
98 - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
99 - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
100 - SPDIF Rx with 4 inputs
101 - HDMI-CEC interface
102 - MDIO Slave interface
103 - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
104 - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
105 - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
106 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
107 - 8- to 14-bit camera interface up to 140 Mbyte/s
108 - 6 analog peripherals
109 - 2 × ADCs with 16-bit max. resolution.
110 - 1 × temperature sensor
111 - 2 × 12-bit D/A converters (1 MHz)
112 - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
114 - Internal or external ADC/DAC reference VREF+
116 - Graphics:
118 - 3D GPU: Vivante® - OpenGL® ES 2.0
119 - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
120 - MIPI® DSI 2 data lanes up to 1 GHz each
122 - Timers:
124 - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
126 - 2 × 16-bit advanced motor control timers
127 - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
128 - 5 × 16-bit low-power timers
129 - RTC with sub-second accuracy and hardware calendar
130 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
131 - 1 × SysTick Cortex®-M4 timer
133 - Hardware acceleration:
135 - AES 128, 192, 256, TDES
136 - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
137 - 2 × true random number generator (3 oscillators each)
138 - 2 × CRC calculation unit
140 - Debug mode:
142 - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
143 - 8-Kbyte embedded trace buffer
144 - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
148 - `STM32MP157C on www.st.com`_
149 - `STM32MP157C reference manual`_
157 +-----------+------------+-------------------------------------+
160 | NVIC | on-chip | nested vector interrupt controller |
161 +-----------+------------+-------------------------------------+
162 | GPIO | on-chip | gpio |
163 +-----------+------------+-------------------------------------+
164 | UART | on-chip | serial port-polling; |
165 | | | serial port-interrupt |
166 +-----------+------------+-------------------------------------+
167 | PINMUX | on-chip | pinmux |
168 +-----------+------------+-------------------------------------+
169 | I2C | on-chip | i2c |
170 +-----------+------------+-------------------------------------+
171 | SPI | on-chip | spi |
172 +-----------+------------+-------------------------------------+
181 STM32MP157C-DK2 Discovery Board schematic is available here:
186 ----------------------------------
188 - USART_3 TX/RX : PB10/PB12 (UART console)
189 - UART_7 TX/RX : PE8/PE7 (Arduino Serial)
190 - I2C5 SCL/SDA : PA11/PA12 (Arduino I2C)
191 - SPI4 SCK/MISO/MOSI : PE12/PE13/PE14 (Arduino SPI)
192 - SPI5 SCK/MISO/MOSI : PF7/PF8/PF9
195 ------------
197 The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
201 -----------
203 The STM32MP157C-DK2 Discovery board has 8 U(S)ARTs.
205 by the Linux Remoteproc Framework on Cortex®-A7 core. In order to keep the UART7
214 The STM32MP157C doesn't have QSPI flash for the Cortex®-M4 and it needs to be
215 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
216 Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.
217 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
220 The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
222 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
224 +------------+-----------------------+------------------------+----------------+
225 | Region | Cortex®-A7 | Cortex®-M4 | Size |
227 | RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB |
228 +------------+-----------------------+------------------------+----------------+
229 | MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB |
230 +------------+-----------------------+------------------------+----------------+
231 | DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB |
232 +------------+-----------------------+------------------------+----------------+
235 Refer to `stm32mp157c boot Cortex-M4 firmware`_ wiki page for instruction
236 to load and start the Cortex-M4 firmware.
243 environment. The firmware must first be loaded by the Cortex®-A7. Developer
248 - Build the sample:
250 .. code-block:: console
252 west build -b stm32mp157c_dk2 samples/hello_world
254 - Copy the firmware on the target filesystem, load it and start it (`stm32mp157c boot Cortex-M4 fir…
255 - Attach to the target:
257 .. code-block:: console
262 …en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/…
268 https://www.st.com/resource/en/schematic_pack/mb1272-dk2-c01_schematic.pdf
271 …w.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp…
279 .. _stm32mp157c boot Cortex-M4 firmware: