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10 multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4
11 core. Zephyr OS is ported to run on the Cortex®-M4 core.
13 - Board features:
15 - PMIC: STPMIC1A
16 - RAM: 1024 Mbyte @ 533MHz
17 - Storage:
19 - eMMC: v4.51: 8 Gbyte
20 - QSPI: 2Mbyte
21 - EEPROM: 128 byte
22 - microSD Socket: UHS-1 v3.01
23 - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant
24 - Wireless:
26 - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac
27 - Bluetooth: v4.2 (BR/EDR/BLE)
28 - USB:
30 - Host - 2x type A, 2.0 high-speed
31 - OTG: - 1x type micro-AB, 2.0 high-speed
32 - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4
33 - Connectors:
35 - 40-Pin Low Speed Header
36 - 60-Pin High Speed Header
37 - LEDs:
39 - 4x Green user LEDs
40 - 1x Blue Bluetooth LED
41 - 1x Yellow WiFi LED
42 - 1x Red power supply LED
56 - Core:
58 - 32-bit dual-core Arm® Cortex®-A7
60 - L1 32-Kbyte I / 32-Kbyte D for each core
61 - 256-Kbyte unified level 2 cache
62 - Arm® NEON™
64 - 32-bit Arm® Cortex®-M4 with FPU/MPU
66 - Up to 209 MHz (Up to 703 CoreMark®)
68 - Memories:
70 - External DDR memory up to 1 Gbyte.
71 - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +
73 - Dual mode Quad-SPI memory interface
74 - Flexible external memory controller with up to 16-bit data bus
76 - Clock management:
78 - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
80 - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
81 - 6 × PLLs with fractional mode
83 - General-purpose input/outputs:
85 - Up to 176 I/O ports with interrupt capability
87 - Interconnect matrix
89 - 3 DMA controllers
91 - Communication peripherals:
93 - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
94 - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
95 - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
96 - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
97 - SPDIF Rx with 4 inputs
98 - HDMI-CEC interface
99 - MDIO Slave interface
100 - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
101 - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
102 - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
103 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
104 - 8- to 14-bit camera interface up to 140 Mbyte/s
105 - 6 analog peripherals
106 - 2 × ADCs with 16-bit max. resolution.
107 - 1 × temperature sensor
108 - 2 × 12-bit D/A converters (1 MHz)
109 - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
111 - Internal or external ADC/DAC reference VREF+
113 - Graphics:
115 - 3D GPU: Vivante® - OpenGL® ES 2.0
116 - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
117 - MIPI® DSI 2 data lanes up to 1 GHz each
119 - Timers:
121 - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
123 - 2 × 16-bit advanced motor control timers
124 - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
125 - 5 × 16-bit low-power timers
126 - RTC with sub-second accuracy and hardware calendar
127 - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
128 - 1 × SysTick Cortex®-M4 timer
130 - Hardware acceleration:
132 - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
133 - 2 × true random number generator (3 oscillators each)
134 - 2 × CRC calculation unit
136 - Debug mode:
138 - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
139 - 8-Kbyte embedded trace buffer
140 - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
144 - `STM32MP157A on www.st.com`_
145 - `STM32MP157A reference manual`_
153 +-----------+------------+-------------------------------------+
156 | NVIC | on-chip | nested vector interrupt controller |
157 +-----------+------------+-------------------------------------+
158 | GPIO | on-chip | gpio |
159 +-----------+------------+-------------------------------------+
160 | UART | on-chip | serial port-polling; |
161 | | | serial port-interrupt |
162 +-----------+------------+-------------------------------------+
163 | PINMUX | on-chip | pinmux |
164 +-----------+------------+-------------------------------------+
178 ----------------------------------
180 - UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console)
181 - UART_4 TX/RX : PD1/PB2
184 ------------
186 The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value
190 -----------
194 on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to
203 The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be
204 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
205 Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.
206 The Cortex®-A7 can perform these steps at bootloader level or after the Linux
209 The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
211 These are the memory mappings for Cortex®-A7 and Cortex®-M4:
213 +------------+-----------------------+------------------------+----------------+
214 | Region | Cortex®-A7 | Cortex®-M4 | Size |
216 | RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB |
217 +------------+-----------------------+------------------------+----------------+
218 | MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB |
219 +------------+-----------------------+------------------------+----------------+
220 | DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB |
221 +------------+-----------------------+------------------------+----------------+
224 Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction
225 to load and start the Cortex-M4 firmware.
232 environment. The firmware must first be loaded by the Cortex®-A7. Developer
236 ------------
241 - Start up the sdk environment::
243 …source <SDK installation directory>/environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-lin…
245 - Start OpenOCD::
247 …${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f …
251 .. code-block:: console
255 mkdir -p build && cd build
257 # Use cmake to configure a Ninja-based build system:
258 cmake -GNinja -DBOARD=96b_avenger96 ..
267 …w.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp…
273 …https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics…
278 .. _stm32mp157 boot Cortex-M4 firmware: