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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 matching prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
55 compatible: "st,stm32wba-rcc"
[all …]
Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
17 prescaler properties.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-prescaler = <1>;
24 apb2-prescaler = <1>;
81 compatible: "st,stm32-rcc"
83 include: [clock-controller.yaml, base.yaml]
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
Dst,stm32h7-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
[all …]
Dst,stm32f1-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Adds the ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f1-rcc"
11 include: st,stm32-rcc.yaml
14 adc-prescaler:
17 - 2
18 - 4
19 - 6
20 - 8
[all …]
Dst,stm32wb-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 For more description confere st,stm32-rcc.yaml
8 compatible: "st,stm32wb-rcc"
11 - name: st,stm32-rcc.yaml
12 property-blocklist:
13 - ahb-prescaler
16 cpu1-prescaler:
20 - 1
21 - 2
22 - 3
[all …]
Dadi,max32-gcr.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,max32-gcr"
8 include: [clock-controller.yaml, base.yaml]
14 "#clock-cells":
17 sysclk-prescaler:
20 - 1
21 - 2
22 - 4
23 - 8
[all …]
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
26 slow-clock:
35 clksys-prescaler:
39 - 1
40 - 2
41 - 4
[all …]
Dst,stm32h7rs-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
14 "clock-frequency" property.
16 prescaler properties.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
29 Confere st,stm32-rcc binding for information about domain clocks configuration.
31 compatible: "st,stm32h7rs-rcc"
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
52 - 1
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcm/
Dnpcm4.dtsi4 * SPDX-License-Identifier: Apache-2.0
17 reg-io-width = <1>;
23 reg-io-width = <2>;
26 pcc: clock-controller@4000d000 {
27 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
28 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
29 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
30 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
31 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
32 ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
[all …]
/Zephyr-latest/dts/bindings/timer/
Dst,stm32-lptim.yaml2 # SPDX-License-Identifier: Apache-2.0
12 compatible: "st,stm32-lptim"
15 - name: st,stm32-timers.yaml
16 property-blocklist:
18 - resets
19 - st,prescaler
20 - st,countermode
23 st,prescaler:
29 Prescaler allows to achieve higher LPTIM timeout (up to 256s when lptim clocked by LSE)
30 and consequently higher core sleep durations, but impacts the tick precision.
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay4 * SPDX-License-Identifier: Apache-2.0
19 /delete-property/ clock-frequency;
20 /delete-property/ hse-bypass;
33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
44 /delete-property/ div-m;
45 /delete-property/ mul-n;
46 /delete-property/ div-q;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dwb_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwb_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
21 /delete-property/ hsi-div;
26 /delete-property/ msi-range;
30 /delete-property/ div-m;
31 /delete-property/ mul-n;
32 /delete-property/ div-p;
[all …]
Df4_i2s2_pll.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
30 /delete-property/ mul;
31 /delete-property/ div;
32 /delete-property/ prediv;
33 /delete-property/ xtpre;
34 /delete-property/ clocks;
39 /delete-property/ clocks;
40 /delete-property/ clock-frequency;
[all …]
Dl4_i2c1_hsi_lptim1_lse.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
Dl4_i2c1_sysclk_lptim1_lsi.overlay4 * SPDX-License-Identifier: Apache-2.0
13 /delete-property/ hse-bypass;
14 /delete-property/ clock-frequency;
23 /delete-property/ msi-range;
27 /delete-property/ div-m;
28 /delete-property/ mul-n;
29 /delete-property/ div-p;
30 /delete-property/ div-q;
31 /delete-property/ div-r;
32 /delete-property/ clocks;
[all …]
/Zephyr-latest/boards/weact/stm32f405_core/
Dweact_stm32f405_core.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/f4/stm32f405rgtx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 model = "WeAct Studio STM32F405 Core Board";
14 compatible = "weact,stm32f405-core", "st,stm32f405";
18 zephyr,shell-uart = &usart1;
25 compatible = "gpio-leds";
33 compatible = "gpio-keys";
54 clock-frequency = <DT_FREQ_M(8)>;
[all …]
/Zephyr-latest/samples/boards/st/power_mgmt/blinky/
DREADME.rst1 .. zephyr:code-sample:: stm32_pm_blinky
4 Blink an LED using the GPIO API in a low-power context on STM32
13 When setting a prescaler to decrease the lptimer input clock frequency, the system can sleep
16 prescaler of <32>, then the kernel sleep period can reach 65536 * 32/32768 = 64 seconds
19 .. _stm32-pm-blinky-sample-requirements:
26 in core sleep states, as LPTIM (:dtcompatible:`st,stm32-lptim`).
33 .. zephyr-app-commands::
34 :zephyr-app: samples/basic/blinky
40 When LPTIM input clock has a prescaler, longer perdiod (up to 64 seconds)
/Zephyr-latest/dts/bindings/i3c/
Dnuvoton,npcx-i3c.yaml2 # SPDX-License-Identifier: Apache-2.0
11 clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
12 core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
13 apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
14 apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
15 apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
16 apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
30 i3c-scl-hz = <12500000>;
31 i3c-od-scl-hz = <4170000>;
36 compatible: "nuvoton,npcx-i3c"
[all …]
/Zephyr-latest/tests/drivers/can/timing/src/
Dmain.c2 * Copyright (c) 2022-2024 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
55 /* CiA 601-2 recommended data phase bitrates */
78 const uint32_t ts = 1 + timing->prop_seg + timing->phase_seg1 + timing->phase_seg2; in assert_bitrate_correct()
83 zassert_not_equal(timing->prescaler, 0, "prescaler is zero"); in assert_bitrate_correct()
86 zassert_equal(err, 0, "failed to get core CAN clock"); in assert_bitrate_correct()
88 bitrate_calc = core_clock / timing->prescaler / ts; in assert_bitrate_correct()
105 zassert_true(timing->sjw <= max->sjw, "sjw exceeds max"); in assert_timing_within_bounds()
106 zassert_true(timing->prop_seg <= max->prop_seg, "prop_seg exceeds max"); in assert_timing_within_bounds()
107 zassert_true(timing->phase_seg1 <= max->phase_seg1, "phase_seg1 exceeds max"); in assert_timing_within_bounds()
[all …]
/Zephyr-latest/drivers/can/
Dcan_fake.c4 * SPDX-License-Identifier: Apache-2.0
64 /* Recommended CAN clock from CiA 601-3 */ in fake_can_get_core_clock_delegate()
91 /* Re-install default delegate for reporting the core clock */ in fake_can_reset_rule_before()
100 /* Install default delegate for reporting the core clock */ in fake_can_init()
122 /* Recommended configuration ranges from CiA 601-2 */
128 .prescaler = 1
135 .prescaler = 32
139 /* Recommended configuration ranges from CiA 601-2 */
145 .prescaler = 1
152 .prescaler = 32

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