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/Zephyr-latest/tests/drivers/counter/counter_basic_api/boards/
Dda1469x_dk_pro.overlay2 clock-src = <&lp_clk>;
8 clock-src = <&divn_clk>;
14 clock-src = <&lp_clk>;
20 clock-src = <&divn_clk>;
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dflash_clock_setup.c3 * SPDX-License-Identifier: Apache-2.0
13 /* Enable FLEXSPI clock again */ in flash_deinit()
14 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK; in flash_deinit()
17 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
20 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && in flash_deinit()
21 (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { in flash_deinit()
24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
33 /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, in flash_init()
36 base->DLLCR[0] = 0x1U; in flash_init()
39 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_adc.c4 * SPDX-License-Identifier: Apache-2.0
33 #define PERIPHCLK_ADC (-1)
35 #define GET_ADC_SOURCE() (-1);
38 /* Not all the stm32 series have all the clock sources */
46 #define ADC_SOURCE_PLL (-1)
54 #define ADC_SOURCE_SYSCLK (-1)
69 "ADC1 gating clock should be off initially"); in ZTEST()
71 /* Test clock_on(gating clock) */ in ZTEST()
74 zassert_true((r == 0), "Could not enable ADC1 gating clock"); in ZTEST()
77 zassert_true(ADC_IS_CLK_ENABLED(), "[HAL] ADC1 gating clock should be on"); in ZTEST()
[all …]
Dtest_stm32_clock_configuration_lptim.c4 * SPDX-License-Identifier: Apache-2.0
32 /* Test clock_on(gating clock) */ in ZTEST()
35 zassert_true((r == 0), "Could not enable LPTIM gating clock"); in ZTEST()
37 zassert_true(__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clock should be on"); in ZTEST()
38 TC_PRINT("LPTIM1 gating clock on\n"); in ZTEST()
45 zassert_true((r == 0), "Could not enable LPTIM1 domain clock"); in ZTEST()
46 TC_PRINT("LPTIM1 source clock configured\n"); in ZTEST()
48 /* Test clock source */ in ZTEST()
53 "Expected LPTIM1 src: LSE (0x%lx). Actual LPTIM1 src: 0x%x", in ZTEST()
57 "Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x", in ZTEST()
[all …]
Dtest_stm32_clock_configuration_i2c.c4 * SPDX-License-Identifier: Apache-2.0
37 zassert_true((r == 0), "Could not enable I2C domain clock"); in i2c_set_clock()
38 TC_PRINT("I2C1 domain clock configured\n"); in i2c_set_clock()
40 /* Test clock source */ in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
45 "Expected I2C src: HSI (0x%lx). Actual I2C src: 0x%x", in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
49 "Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x", in i2c_set_clock()
58 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on"); in i2c_set_clock()
71 TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq); in i2c_set_clock()
[all …]
Dtest_stm32_clock_configuration_sdmmc.c4 * SPDX-License-Identifier: Apache-2.0
20 #warning "Missing clock 48MHz"
24 #warning "Missing clock I2S PLL clock"
37 /* Test clock_on(gating clock) */ in ZTEST()
40 zassert_true((r == 0), "Could not enable SDMMC gating clock"); in ZTEST()
42 zassert_true(__HAL_RCC_SDIO_IS_CLK_ENABLED(), "SDMMC gating clock should be on"); in ZTEST()
43 TC_PRINT("SDMMC gating clock on\n"); in ZTEST()
45 zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(sdmmc1)) > 1), "No domain clock defined in dts"); in ZTEST()
48 /* CLK 48 is enabled through the clock-mux */ in ZTEST()
49 zassert_true(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk48)), "No clock 48MHz"); in ZTEST()
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/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c4 * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
30 * 32KHz period counter minimum for pass/fail: 16-bit
31 * 32KHz period counter maximum for pass/fail: 16-bit
32 * 32KHz duty cycle variation max for pass/fail: 16-bit
33 * 32KHz valid count minimum: 8-bit
37 * One 32KHz clock pulse = 1464.84 48 MHz counts.
99 uint32_t RSVD4[(0x00c0 - 0x0094) / 4];
131 /* VBAT powered hardware registers related to clock configuration */
162 /* MEC172x Select source of peripheral 32KHz clock */
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Dclock_control_ast10x0.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/ast10x0_clock.h>
22 * - Each bit in these registers controls a clock gate
23 * - Write '1' to a bit: turn OFF the corresponding clock
24 * - Write '0' to a bit: no effect
26 * - Write '1' to a bit: clear the corresponding bit in CLK_STOP_CTRL0/1.
27 * (turn ON the corresponding clock)
50 #define DEV_CFG(dev) ((const struct clock_aspeed_config *const)(dev)->config)
54 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_on()
64 clk_gate -= ASPEED_CLK_GRP_1_OFFSET; in aspeed_clock_control_on()
[all …]
/Zephyr-latest/tests/kernel/common/
DCMakeLists.txt1 # SPDX-License-Identifier: Apache-2.0
9 src/printk.c
13 src/atomic.c
14 src/bitarray.c
15 src/byteorder.c
16 src/clock.c
17 src/main.c
18 src/timeout_order.c
19 src/multilib.c
20 src/errno.c
[all …]
/Zephyr-latest/dts/bindings/clock/
Despressif,esp32-rtc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ESP32 RTC (Power & Clock Controller Module) Module
6 compatible: "espressif,esp32-rtc"
8 include: [clock-controller.yaml, base.yaml]
14 fast-clk-src:
18 RTC fast clock source.
19 - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
23 - 0
24 - 1
[all …]
Dmicrochip,xec-pcr.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
28 description: 32 KHz clock source for PLL
[all …]
Drenesas,smartbond-lp-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Smartbond low power clock
6 compatible: "renesas,smartbond-lp-clk"
9 - name: base.yaml
10 property-allowlist:
11 - status
12 - compatible
15 clock-src:
18 Low power clock source.
Drenesas,smartbond-sys-clock.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Smartbond system clock
6 compatible: "renesas,smartbond-sys-clk"
9 - name: base.yaml
10 property-allowlist:
11 - status
12 - compatible
15 clock-src:
18 System clock source.
/Zephyr-latest/samples/drivers/clock_control_xec/boards/
Dmec1501modular_assy6885.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
24 /* 32KHZ_IN is a clock source with debug */
[all …]
Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
24 /* 32KHZ_IN is a clock source with debug */
[all …]
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
13 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
14 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
15 xtal-single-ended;
16 internal-osc-disable;
19 pinctrl-0 = <&tst_clk_out_gpio060 &clk_32khz_out_gpio221>;
21 /* 32KHZ_IN is a clock source and no debug */
22 /* pinctrl-0 = <&clk_32khz_in_gpio165>; */
24 /* 32KHZ_IN is a clock source with debug */
[all …]
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c3 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
6 * Copyright (c) 2014-2015 Wind River Systems, Inc.
9 * SPDX-License-Identifier: Apache-2.0
33 /* System Clock configuration */
35 "Invalid SCG bus clock divider value");
37 "Invalid SCG core clock divider value");
43 .src = kSCG_SysClkSrcSirc,
45 .src = kSCG_SysClkSrcFirc,
49 /* Slow Internal Reference Clock (SIRC) configuration */
60 #error Invalid SCG SIRC clock frequency
[all …]
/Zephyr-latest/soc/nxp/mcx/mcxw/
Dsoc.c2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
24 /* Unlock Reference Clock Status Registers to allow writes */ in clock_init()
45 /* Select the Real Time Clock (RTC) source as OSC32K */ in clock_init()
53 /* Re-enable monitor */ in clock_init()
63 .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ in clock_init()
70 .src = (uint32_t)kSCG_SysClkSrcSirc, in clock_init()
79 } while (cur_config.src != sys_clk_safe_config_source.src); in clock_init()
84 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ in clock_init()
85 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ in clock_init()
[all …]
/Zephyr-latest/dts/bindings/phy/
Drenesas,ra-usbphyc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,ra-usbphyc"
8 include: phy-controller.yaml
11 clock:
14 Clock source for PHY clock in case internal clock is using
16 phys-clock-src:
19 - "internal"
20 - "xtal"
22 Select clock source for PHY clock as XTAL or use internal clock
24 "#phy-cells":
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dflash_clock_setup.c3 * SPDX-License-Identifier: Apache-2.0
20 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && in flash_deinit()
21 (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { in flash_deinit()
24 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in flash_deinit()
35 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in flash_init()
37 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in flash_init()
38 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) { in flash_init()
42 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) { in flash_init()
43 lastStatus = base->STS2; in flash_init()
46 if (((base->FLSHCR0[0] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0) || in flash_init()
[all …]
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
34 /* System Clock configuration */
36 "Invalid SCG slow clock divider value");
38 "Invalid SCG bus clock divider value");
40 /* Core divider range is 1 to 4 with SPLL as clock source */
42 "Invalid SCG core clock divider value");
45 "Invalid SCG core clock divider value");
52 .src = kSCG_SysClkSrcSysOsc,
[all …]
/Zephyr-latest/soc/nxp/rw/
Dflexspi_clock_setup.c2 * Copyright 2022-2023 NXP
3 * SPDX-License-Identifier: Apache-2.0
15 * @brief Set flexspi clock to given frequency
19 * is used by the clock control framework to set the clock frequency of
29 /* Get the root clock rate: FlexSPI clock * divisor */ in flexspi_clock_set_freq()
30 root_rate = ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1) * in flexspi_clock_set_freq()
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
45 set_flexspi_clock(FLEXSPI, (CLKCTL0->FLEXSPIFCLKSEL & in flexspi_clock_set_freq()
58 * @brief Set flexspi clock
60 void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in set_flexspi_clock() argument
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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
24 /* Not device related, but keep it to ensure core clock config is correct */
56 /* Select domain_clk as device source clock */ in ZTEST()
67 "Expected SPI src: PLL1 Q (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected SPI src: PLL2 P (0x%x). Actual: 0x%x", in ZTEST()
75 "Expected SPI src: PLL3 P (0x%x). Actual: 0x%x", in ZTEST()
79 "Expected SPI src: PERCLK (0x%x). Actual: 0x%x", in ZTEST()
92 "Expected PERCK src: HSI_KER (0x%x). Actual: 0x%x", in ZTEST()
96 "Expected PERCK src: CSI_KER (0x%x). Actual: 0x%x", in ZTEST()
100 "Expected PERCK src: HSE (0x%x). Actual: 0x%x", in ZTEST()
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c4 * SPDX-License-Identifier: Apache-2.0
24 /* Not device related, but keep it to ensure core clock config is correct */
47 zassert_true((r == 0), "Could not enable SPI gating clock"); in ZTEST()
49 zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on"); in ZTEST()
50 TC_PRINT("SPI1 gating clock on\n"); in ZTEST()
65 "Expected SPI src: HSI (0x%x). Actual: 0x%x", in ZTEST()
69 "Expected SPI src: SYSCLK (0x%x). Actual: 0x%x", in ZTEST()
72 zassert_true(1, "Unexpected clk src (0x%x)", spi1_actual_domain_clk); in ZTEST()
86 /* No domain clock available, get rate from gating clock */ in ZTEST()
88 /* Test get_rate(gating clock) */ in ZTEST()
[all …]
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Dxmc47_relax_kit.overlay4 * SPDX-License-Identifier: Apache-2.0
8 * This sample requires several connections listed below. However, no external pull-ups
14 #include <zephyr/dt-bindings/i2c/i2c.h>
17 compatible = "infineon,xmc4xxx-i2c";
21 /delete-property/ miso-src;
23 clock-frequency = <I2C_BITRATE_STANDARD>;
24 pinctrl-0 = <&i2c_scl_p5_2_u2c0 &i2c_sda_dx0_p3_7_u2c0 &i2c_sda_dout0_p3_8_u2c0>;
25 pinctrl-names = "default";
27 scl-src = "DX1A";
28 sda-src = "DX0C";
[all …]

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