Lines Matching +full:clock +full:- +full:src

3  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
6  * Copyright (c) 2014-2015 Wind River Systems, Inc.
9  * SPDX-License-Identifier: Apache-2.0
33 /* System Clock configuration */
35 		    "Invalid SCG bus clock divider value");
37 		    "Invalid SCG core clock divider value");
43 	.src     = kSCG_SysClkSrcSirc,
45 	.src     = kSCG_SysClkSrcFirc,
49 /* Slow Internal Reference Clock (SIRC) configuration */
60 #error Invalid SCG SIRC clock frequency
64 /* Fast Internal Reference Clock (FIRC) configuration */
79 #error Invalid SCG FIRC clock frequency
89 		.src     = kSCG_SysClkSrcSirc  in clk_init()
100 	} while (current.src != scg_sys_clk_config_safe.src);  in clk_init()
107 	} while (current.src != scg_sys_clk_config.src);  in clk_init()