Lines Matching +full:clock +full:- +full:src

2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14   core-clock-div:
17     description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19   slow-clock-div:
22       PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25   pll-32k-src:
28     description: 32 KHz clock source for PLL
30   periph-32k-src:
33     description: 32 KHz clock source for peripherals
35   xtal-single-ended:
39   clk32kmon-period-min:
43       32KHz clock monitor minimum valid 32KHz period in 48MHz units
45   clk32kmon-period-max:
49       32KHz clock monitor maximum valid 32KHz period in 48MHz units
51   clk32kmon-duty-cycle-var-max:
58   clk32kmon-valid-min:
64   xtal-enable-delay-ms:
69       Delay in milliseconds after crystal is enabled and clock monitor is
72   pll-lock-timeout-ms:
77       Timeout in milliseconds waiting for PLL to lock to new clock source.
79   clkmon-bypass:
81     description: Bypass clkmon check of crystal or XTAL2 single-ended clock.
83   internal-osc-disable:
90   "#clock-cells":
93 clock-cells:
94   - regidx
95   - bitpos
96   - domain