Lines Matching +full:clock +full:- +full:src
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/ast10x0_clock.h>
22 * - Each bit in these registers controls a clock gate
23 * - Write '1' to a bit: turn OFF the corresponding clock
24 * - Write '0' to a bit: no effect
26 * - Write '1' to a bit: clear the corresponding bit in CLK_STOP_CTRL0/1.
27 * (turn ON the corresponding clock)
50 #define DEV_CFG(dev) ((const struct clock_aspeed_config *const)(dev)->config)
54 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_on()
64 clk_gate -= ASPEED_CLK_GRP_1_OFFSET; in aspeed_clock_control_on()
75 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_off()
85 clk_gate -= ASPEED_CLK_GRP_1_OFFSET; in aspeed_clock_control_off()
97 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_get_rate()
99 uint32_t reg, src, clk_div; in aspeed_clock_control_get_rate() local
108 src = HPLL_FREQ; in aspeed_clock_control_get_rate()
110 src = MHZ(480); in aspeed_clock_control_get_rate()
113 *rate = src / clk_div; in aspeed_clock_control_get_rate()
116 src = HPLL_FREQ; in aspeed_clock_control_get_rate()
119 *rate = src / clk_div; in aspeed_clock_control_get_rate()
122 src = HPLL_FREQ; in aspeed_clock_control_get_rate()
125 *rate = src / clk_div; in aspeed_clock_control_get_rate()
143 return -EINVAL; in aspeed_clock_control_get_rate()