Lines Matching +full:clock +full:- +full:src

2  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5  * Copyright (c) 2014-2015 Wind River Systems, Inc.
8  * SPDX-License-Identifier: Apache-2.0
34 /* System Clock configuration */
36 		    "Invalid SCG slow clock divider value");
38 		    "Invalid SCG bus clock divider value");
40 /* Core divider range is 1 to 4 with SPLL as clock source */
42 		    "Invalid SCG core clock divider value");
45 		    "Invalid SCG core clock divider value");
52 	.src     = kSCG_SysClkSrcSysOsc,
54 	.src     = kSCG_SysClkSrcSirc,
56 	.src     = kSCG_SysClkSrcFirc,
58 	.src     = kSCG_SysClkSrcSysPll,
60 #error Invalid SCG core clock source
80 /* Slow Internal Reference Clock (SIRC) configuration */
94 #error Invalid SCG SIRC clock frequency
98 /* Fast Internal Reference Clock (FIRC) configuration */
116 #error Invalid SCG FIRC clock frequency
121 /* System Phase-Locked Loop (SPLL) configuration */
138 	.src         = kSCG_SysPllSrcSysOsc,
140 	.src         = kSCG_SysPllSrcFirc,
142 #error Invalid SCG PLL clock source
144 	.prediv      = (SCG_CLOCK_DIV(pll) - 1U),
145 	.mult        = (SCG_CLOCK_MULT(pll) - 16U)
154 		.src     = kSCG_SysClkSrcSirc  in clk_init()
170 	} while (current.src != scg_sys_clk_config_safe.src);  in clk_init()
180 	} while (current.src != scg_sys_clk_config.src);  in clk_init()
250 	 * Note that the KE1xF does not implement the optional ARMv7-M memory  in soc_early_init_hook()
252 	 * Cortex-M4 core.  Instead, the processor includes its own MPU module.  in soc_early_init_hook()
254 	temp_reg = SYSMPU->CESR;  in soc_early_init_hook()
257 	SYSMPU->CESR = temp_reg;  in soc_early_init_hook()
288 	WDOG->CNT = WDOG_UPDATE_KEY;  in z_arm_watchdog_init()
289 	while (!(WDOG->CS & WDOG_CS_ULK_MASK)) {  in z_arm_watchdog_init()
297 	WDOG->TOVAL = CONFIG_WDOG_INITIAL_TIMEOUT >> 1;  in z_arm_watchdog_init()
298 	WDOG->CS = WDOG_CS_PRES(1) | WDOG_CS_CLK(1) | WDOG_CS_WAIT(1) |  in z_arm_watchdog_init()
301 	while (!(WDOG->CS & WDOG_CS_RCS_MASK)) {  in z_arm_watchdog_init()