Lines Matching +full:clock +full:- +full:src
2 * Copyright 2023-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
24 /* Unlock Reference Clock Status Registers to allow writes */ in clock_init()
45 /* Select the Real Time Clock (RTC) source as OSC32K */ in clock_init()
53 /* Re-enable monitor */ in clock_init()
63 .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ in clock_init()
70 .src = (uint32_t)kSCG_SysClkSrcSirc, in clock_init()
79 } while (cur_config.src != sys_clk_safe_config_source.src); in clock_init()
84 .divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */ in clock_init()
85 .divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */ in clock_init()
86 .divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */ in clock_init()
87 .src = (uint32_t)kSCG_SysClkSrcFirc, /* Select Fast IRC as System Clock */ in clock_init()
91 /* Wait for clock source switch to finish */ in clock_init()
94 } while (cur_config.src != sys_clk_config.src); in clock_init()
98 /* OSC-RF / System Oscillator Configuration */ in clock_init()
105 /* Init OSC-RF / SOSC */ in clock_init()
109 /* Slow internal reference clock (SIRC) configuration */ in clock_init()
200 base->STATUSA |= VBAT_STATUSA_POR_DET_MASK; in vbat_init()
210 /* Initialize system clock to 96 MHz */ in soc_early_init_hook()