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/Zephyr-latest/samples/subsys/input/input_dump/boards/
Desp32_devkitc_wroom_procpu.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
8 #include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
[all …]
Desp32_devkitc_wrover_procpu.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
8 #include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
[all …]
Desp32s2_saola.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
8 #include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
[all …]
Desp32s3_devkitm_procpu.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
8 #include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
14 channel-num = <9>;
15 channel-sens = <20>;
20 channel-num = <8>;
21 channel-sens = <20>;
26 channel-num = <6>;
27 channel-sens = <20>;
32 channel-num = <4>;
[all …]
/Zephyr-latest/dts/bindings/i2c/
Dite,common-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [i2c-controller.yaml, pinctrl-device.yaml]
15 port-num:
19 - 0
20 - 1
21 - 2
22 - 3
23 - 4
24 - 5
33 channel-switch-sel:
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/Zephyr-latest/tests/bluetooth/tester/src/
Dbtp_l2cap.c1 /* l2cap.c - Bluetooth L2CAP Tester */
6 * SPDX-License-Identifier: Apache-2.0
35 static struct channel { struct
36 uint8_t chan_id; /* Internal number that identifies L2CAP channel. */ argument
58 struct channel *chan = CONTAINER_OF(l2cap_le_chan, struct channel, le); in seg_recv_cb() argument
60 ev = (void *)chan->recv_cb_buf; in seg_recv_cb()
61 memcpy(&ev->data[seg_offset], seg->data, seg->len); in seg_recv_cb()
64 if (seg_offset + seg->len == sdu_len) { in seg_recv_cb()
65 ev->chan_id = chan->chan_id; in seg_recv_cb()
66 ev->data_length = sys_cpu_to_le16(sdu_len); in seg_recv_cb()
[all …]
/Zephyr-latest/dts/bindings/dma/
Dnxp,lpc-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,lpc-dma"
8 include: dma-controller.yaml
17 dma-channels:
20 nxp,dma-num-of-otrigs:
22 description: Number of Inputmux connections a DMA channel can receive from
24 nxp,dma-otrig-base-address:
28 nxp,dma-itrig-base-address:
30 description: DMA Channel Selection Address used for receiving signals
32 "#dma-cells":
[all …]
Dxilinx,axi-dma-base.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: dma-controller.yaml
21 interrupt-parent:
26 type: phandle-array
28 clock-frequency:
36 - 32
37 - 64
39 axistream-connected:
43 The axistream-connected and axistream-control-connected properties can easily cause circular
48 axistream-control-connected:
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/Zephyr-latest/dts/bindings/input/
Despressif,esp32-touch-sensor.yaml2 # SPDX-License-Identifier: Apache-2.0
8 sensor is defined in a child node of the touch-sensor node and defines a specific key
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 #include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
17 compatible = "espressif,esp32-touch";
20 debounce-interval-ms = <30>;
21 href-microvolt = <27000000>;
22 lref-microvolt = <500000>;
23 href-atten-microvolt = <1000000>;
24 filter-mode = <ESP32_TOUCH_FILTER_MODE_IIR_16>;
[all …]
/Zephyr-latest/dts/bindings/dac/
Dgd,gd32-dac.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "gd,gd32-dac"
8 include: [dac-controller.yaml, reset-device.yaml, pinctrl-device.yaml]
20 num-channels:
25 reset-val:
30 "#io-channel-cells":
33 io-channel-cells:
34 - output
/Zephyr-latest/dts/arm/nxp/
Dnxp_rw6xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
10 #include <dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/power/nxp_rw_pmu.h>
12 #include <dt-bindings/adc/nxp,gau-adc.h>
13 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
Dnxp_rt5xx_common.dtsi2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
14 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
15 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
[all …]
Dnxp_rt6xx_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
Dnxp_lpc55S6x_common.dtsi5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
15 #include <arm/armv8-m.dtsi>
16 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
24 zephyr,flash-controller = &iap;
[all …]
Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
60 /* Each channel has separate interrupt entry */
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
[all …]
Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/counter/
Datmel,sam-tc.yaml1 # SPDX-License-Identifier: Apache-2.0
5 compatible: "atmel,sam-tc"
8 - name: base.yaml
9 - name: pinctrl-device.yaml
21 channel:
24 Timer / Counter channel to use, channel 0 is the default.
25 Valid range: 0 - 2
30 Clock source selection as defined by TCCLKS bit-field of TC_CMR
40 reg-cmr:
43 Alternate value of the CMR (Channel Mode Register) register.
[all …]
/Zephyr-latest/dts/bindings/rtc/
Dnordic,nrf-rtc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF RTC (Real-Time Counter)
6 compatible: "nordic,nrf-rtc"
14 cc-num:
23 # through PPI channel which ensures precise timing. If disabled then
26 ppi-wrap:
32 # channel
33 fixed-top:
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f350.dtsi4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-dac";
17 num-channels = <1>;
19 #io-channel-cells = <1>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l053.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 clk_hsi48: clk-hsi48 {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <DT_FREQ_M(48)>;
21 compatible = "st,stm32l053", "st,stm32l0", "simple-bus";
24 compatible = "st,stm32-usb";
27 interrupt-names = "usb";
28 num-bidir-endpoints = <8>;
29 ram-size = <1024>;
[all …]
Dstm32l072.dtsi4 * SPDX-License-Identifier: Apache-2.0
15 clk_hsi48: clk-hsi48 {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-frequency = <DT_FREQ_M(48)>;
24 compatible = "st,stm32l072", "st,stm32l0", "simple-bus";
27 compatible = "st,stm32-usb";
30 interrupt-names = "usb";
31 num-bidir-endpoints = <8>;
32 ram-size = <1024>;
[all …]
/Zephyr-latest/dts/arm/nordic/
Dnrf51822.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv6-m.dtsi>
5 #include <zephyr/dt-bindings/adc/nrf-adc.h>
9 zephyr,bt-hci = &bt_hci_controller;
11 zephyr,flash-controller = &flash_controller;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0";
27 compatible = "nordic,nrf-ficr";
29 #nordic,ficr-cells = <1>;
[all …]
/Zephyr-latest/include/zephyr/bluetooth/classic/
Da2dp_codec_sbc.h2 * @brief Advance Audio Distribution Profile - SBC Codec header.
5 * SPDX-License-Identifier: Apache-2.0
6 * Copyright (c) 2015-2016 Intel Corporation
13 * http://www.apache.org/licenses/LICENSE-2.0
34 /* Channel Mode */
54 #define BT_A2DP_SBC_SAMP_FREQ(cap) ((cap->config[0] >> 4) & 0x0f)
55 #define BT_A2DP_SBC_CHAN_MODE(cap) ((cap->config[0]) & 0x0f)
56 #define BT_A2DP_SBC_BLK_LEN(cap) ((cap->config[1] >> 4) & 0x0f)
57 #define BT_A2DP_SBC_SUB_BAND(cap) ((cap->config[1] >> 2) & 0x03)
58 #define BT_A2DP_SBC_ALLOC_MTHD(cap) ((cap->config[1]) & 0x03)
[all …]
/Zephyr-latest/dts/arm/st/f4/
Dstm32f446.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
14 compatible = "st,stm32f411-plli2s-clock";
19 compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
22 compatible = "st,stm32-i2s";
23 #address-cells = <1>;
24 #size-cells = <0>;
30 dma-names = "tx", "rx";
35 compatible = "st,stm32-usart", "st,stm32-uart";
[all …]
/Zephyr-latest/dts/arm/ti/
Dcc32xx.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/adc.h>
6 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #define INT_ADCCH0 30 // ADC channel 0
13 #define INT_ADCCH1 31 // ADC channel 1
14 #define INT_ADCCH2 32 // ADC channel 2
15 #define INT_ADCCH3 33 // ADC channel 3
20 #define EXP_UARTA0 (INT_UARTA0 - 16)
[all …]

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