1# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
2# SPDX-License-Identifier: Apache-2.0
3
4description: Xilinx AXI DMA LogiCORE IP controller
5
6include: dma-controller.yaml
7
8# multiple "compatible" properties match the same driver and options
9
10properties:
11  reg:
12    type: array
13    description: DMA Control registers
14    required: true
15
16  interrupts:
17    type: array
18    description: TX IRQ number followed by RX IRQ number
19    required: true
20
21  interrupt-parent:
22    type: phandle
23    description: Interrupt controller that the DMA is connected to
24
25  clocks:
26    type: phandle-array
27
28  clock-frequency:
29    type: int
30
31  xlnx,addrwidth:
32    type: int
33    required: true
34    description: DMA address width (64 or 32 bit)
35    enum:
36      - 32
37      - 64
38
39  axistream-connected:
40    type: phandle
41    description: |
42      Handle to connected node, e.g., AXI Ethernet controller.
43      The axistream-connected and axistream-control-connected properties can easily cause circular
44      dependencies, if they are provided at the second device as well.
45      In this case, the python device tree script fails to assign ordinals, causing build failure.
46      I suggest you do not provide them at the DMA.
47
48  axistream-control-connected:
49    type: phandle
50    description: Handle to connected control node, e.g., AXI Ethernet controller
51
52  xlnx,include-dre:
53    type: boolean
54    description: Data realignment engine activated. This enables unaligned DMA transfers.
55
56  xlnx,num-queues:
57    type: int
58    description: Number of queues per channel.
59