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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg21-pinctrl.h113 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
122 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
125 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
126 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
127 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
128 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
129 #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
134 #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
143 #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
146 #define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0)
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Dxg22-pinctrl.h129 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
134 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
135 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
136 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
137 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
141 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
146 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
147 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
148 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
149 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
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Dxg24-pinctrl.h158 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
168 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
174 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
181 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
182 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
183 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
184 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
185 #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
186 #define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5)
191 #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
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Dxg27-pinctrl.h133 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
142 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
147 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
152 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
153 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
154 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
155 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
160 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
165 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
166 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
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Dxg23-pinctrl.h175 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
186 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
193 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
200 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
201 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
202 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
203 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
204 #define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4)
205 #define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5)
210 #define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3)
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/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_gd32.h10 #define GD32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
13 #define GD32_DMA_CONFIG_PERIPH_WIDTH(config) ((config >> 11) & 0x3)
14 #define GD32_DMA_CONFIG_MEMORY_WIDTH(config) ((config >> 13) & 0x3)
16 #define GD32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
18 #define GD32_DMA_FEATURES_FIFO_THRESHOLD(threshold) (threshold & 0x3)
Ddma_stm32.h61 #define STM32_DMA_CONFIG_DIRECTION(config) ((config >> 6) & 0x3)
69 (1 << ((config >> 11) & 0x3))
73 (1 << ((config >> 13) & 0x3))
77 #define STM32_DMA_CONFIG_PRIORITY(config) ((config >> 16) & 0x3)
81 #define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) (features & 0x3)
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h19 #define LSM6DSV16X_DT_FS_1000DPS 0x3
27 #define LSM6DSV16X_DT_ODR_AT_15Hz 0x3
62 #define LSM6DSV16X_DT_XL_BATCHED_AT_15Hz 0x3
77 #define LSM6DSV16X_DT_GY_BATCHED_AT_15Hz 0x3
92 #define LSM6DSV16X_DT_TEMP_BATCHED_AT_60Hz 0x3
98 #define LSM6DSV16X_DT_SFLP_ODR_AT_120Hz 0x3
106 #define LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY 0x3
/Zephyr-latest/soc/renesas/ra/ra4m1/
Dsoc.c105 .IWDTTOPS = 0x3, .IWDTCKS = 0xf, .IWDTRPES = 0x3, .IWDTRPSS = 0x3,
106 .IWDTRSTIRQS = 0x1, .RSVD2 = 0x1, .IWDTSTPCTL = 0x1, .RSVD3 = 0x3,
108 .WDTTOPS = 0x3, .WDTCKS = 0xf, .WDTRPES = 0x3, .WDTRPSS = 0x3,
112 .RSVD1 = 0x3,
114 .VDSEL1 = 0x3,
115 .RSVD2 = 0x3,
/Zephyr-latest/dts/arm/st/f4/
Dstm32f411.dtsi38 dmas = <&dma2 3 3 0x400 0x3
39 &dma2 2 3 0x400 0x3>;
51 dmas = <&dma2 1 4 0x400 0x3
52 &dma2 0 4 0x400 0x3>;
64 dmas = <&dma2 6 7 0x400 0x3
65 &dma2 5 7 0x400 0x3>;
Dstm32f410.dtsi45 dmas = <&dma2 3 3 0x400 0x3
46 &dma2 2 3 0x400 0x3>;
58 dmas = <&dma1 4 0 0x400 0x3
59 &dma1 3 0 0x400 0x3>;
71 dmas = <&dma2 6 7 0x400 0x3
72 &dma2 5 7 0x400 0x3>;
Dstm32f401.dtsi58 dmas = <&dma1 4 0 0x400 0x3
59 &dma1 3 0 0x400 0x3>;
71 dmas = <&dma1 5 0 0x400 0x3
72 &dma1 0 0 0x400 0x3>;
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_fs26.h73 #define FS26_M_TSD_FLG (0x3)
130 #define VMON_PRE_OV_FS_REACTION_MASK (0x3 << VMON_PRE_OV_FS_REACTION_SHIFT)
137 #define VMON_PRE_UV_FS_REACTION_MASK (0x3 << VMON_PRE_UV_FS_REACTION_SHIFT)
144 #define VMON_CORE_OV_FS_REACTION_MASK (0x3 << VMON_CORE_OV_FS_REACTION_SHIFT)
151 #define VMON_CORE_UV_FS_REACTION_MASK (0x3 << VMON_CORE_UV_FS_REACTION_SHIFT)
158 #define VMON_LDO1_OV_FS_REACTION_MASK (0x3 << VMON_LDO1_OV_FS_REACTION_SHIFT)
165 #define VMON_LDO1_UV_FS_REACTION_MASK (0x3 << VMON_LDO1_UV_FS_REACTION_SHIFT)
172 #define VMON_LDO2_OV_FS_REACTION_MASK (0x3 << VMON_LDO2_OV_FS_REACTION_SHIFT)
179 #define VMON_LDO2_UV_FS_REACTION_MASK (0x3 << VMON_LDO2_UV_FS_REACTION_SHIFT)
188 #define VMON_EXT_OV_FS_REACTION_MASK (0x3 << VMON_EXT_OV_FS_REACTION_SHIFT)
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/Zephyr-latest/arch/arm64/core/
Duserspace.S28 mov x3, x0
38 ldrb w5, [x3, x0]
61 mrs x3, DAIF
80 msr DAIF, x3
85 msr DAIF, x3
97 ldp x2, x3, [sp, ___esf_t_x2_x3_OFFSET]
/Zephyr-latest/soc/nxp/lpc/lpc11u6x/
Dsoc.h42 #define IOCON_PIO_MODE(x) (((x) & 0x3) << 3)
43 #define IOCON_PIO_MODE_MASK IOCON_PIO_MODE(0x3)
50 #define IOCON_PIO_SMODE(x) (((x) & 0x3) << 11)
51 #define IOCON_PIO_SMODE_MASK IOCON_PIO_SMODE(0x3)
91 #define IOCON_PIO_I2CMODE(x) (((x) & 0x3) << 8)
92 #define IOCON_PIO_I2CMODE_MASK IOCON_PIO_I2CMODE(0x3)
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dstm32-pinctrl.h21 #define STM32_AF3 0x3
85 #define STM32_MODER_ANALOG_MODE (0x3 << STM32_MODER_SHIFT)
86 #define STM32_MODER_MASK 0x3
99 #define STM32_OSPEEDR_VERY_HIGH_SPEED (0x3 << STM32_OSPEEDR_SHIFT)
100 #define STM32_OSPEEDR_MASK 0x3
107 #define STM32_PUPDR_MASK 0x3
/Zephyr-latest/samples/subsys/usb/dfu/
DREADME.rst84 I: Primary image: magic=good, swap_type=0x3, copy_done=0x1, image_ok=0x1
85 I: Secondary image: magic=good, swap_type=0x2, copy_done=0x3, image_ok=0x3
101 I: Primary image: magic=good, swap_type=0x2, copy_done=0x1, image_ok=0x3
102 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
105 I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
147 I: Secondary image: magic=good, swap_type=0x3, copy_done=0x3, image_ok=0x1
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Dgd32_dma.h13 #define GD32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
29 #define GD32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
35 #define GD32_DMA_CH_CFG_MEMORY_WIDTH(val) ((val & 0x3) << 13)
44 #define GD32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
Dstm32_dma.h19 #define STM32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6)
36 #define STM32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11)
42 #define STM32_DMA_CH_CFG_MEM_WIDTH(val) ((val & 0x3) << 13)
53 #define STM32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16)
/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma.yaml14 - 0x3: reserved for PERIPH to PERIPH
28 - 0x3: reserved
34 - 0x3: reserved
44 - 0x3: very high
Dst,stm32u5-dma.yaml29 0x3: reserved for PERIPH to PERIPH
40 0x3: reserved
45 0x3: reserved
51 0x3: very high
Dgd,gd32-dma-v1.yaml16 - 0x3: reserved for PERIPH to PERIPH
30 - 0x3: reserved
36 - 0x3: reserved
46 - 0x3: very high
53 - 0x3: 4 word
Dst,stm32-dma-v1.yaml23 0x3: reserved for PERIPH to PERIPH
34 0x3: reserved
39 0x3: reserved
47 0x3: STM32_DMA_PRIORITY_VERY_HIGH: very high
53 0x3: STM32_DMA_FIFO_FULL: full FIFO
/Zephyr-latest/boards/nxp/imx8ulp_evk/
Dimx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi9 pinmux = <0x298c0158 0x4 0x298c09e0 0x3 0x298c0158>;
13 pinmux = <0x298c015c 0x4 0x298c09dc 0x3 0x298c015c>;
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi17 alts = <&scfg 0x00 0x3 1>;
32 alts = <&scfg 0x01 0x3 0>;
58 alts = <&scfg 0x02 0x3 0>;
101 alts = <&scfg 0x04 0x3 0>;
135 alts = <&scfg 0x06 0x3 0>;
161 alts = <&scfg 0x07 0x3 1>;
187 alts = <&scfg 0x08 0x3 1>;
213 alts = <&scfg 0x09 0x3 1>;
256 alts = <&scfg 0x0B 0x3 0>;
276 alts = <&scfg 0x0C 0x3 0>;
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