Lines Matching full:x3
133 #define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
142 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
147 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
152 #define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
153 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
154 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
155 #define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
160 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
165 #define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
166 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
167 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
168 #define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
172 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
177 #define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
178 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
179 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
180 #define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
184 #define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
193 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
198 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
203 #define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
204 #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
205 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
206 #define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
211 #define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3)
220 #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
225 #define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3)
230 #define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0)
231 #define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1)
232 #define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2)
233 #define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3)
237 #define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
246 #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
251 #define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
256 #define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
257 #define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
258 #define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
259 #define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
263 #define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3)
272 #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
277 #define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3)
282 #define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0)
283 #define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1)
284 #define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2)
285 #define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3)
289 #define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
298 #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
303 #define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
308 #define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
309 #define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
310 #define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
311 #define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
315 #define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3)
324 #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
329 #define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3)
334 #define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0)
335 #define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1)
336 #define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2)
337 #define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3)
341 #define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
350 #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
355 #define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
360 #define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
361 #define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
362 #define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
363 #define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
368 #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
373 #define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0)
374 #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
375 #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
376 #define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3)
380 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
385 #define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
386 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
387 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
388 #define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
392 #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
397 #define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0)
398 #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
399 #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
400 #define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3)
405 #define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
414 #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
419 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
424 #define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
425 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
426 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
427 #define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
431 #define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
440 #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
445 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
450 #define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
451 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
452 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
453 #define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
458 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
463 #define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
464 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
465 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
466 #define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
470 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
475 #define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
476 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
477 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
478 #define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
483 #define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
492 #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
497 #define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
506 #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
512 #define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
521 #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
526 #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
531 #define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
532 #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
533 #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
534 #define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
538 #define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
547 #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
552 #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
557 #define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
558 #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
559 #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
560 #define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
564 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
569 #define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
570 #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
571 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
572 #define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
576 #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
581 #define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
582 #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
583 #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
584 #define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
588 #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
593 #define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
594 #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
595 #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
596 #define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
600 #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
605 #define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
606 #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
607 #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
608 #define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
612 #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
617 #define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
618 #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
619 #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
620 #define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
624 #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
629 #define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
630 #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
631 #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
632 #define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
636 #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
641 #define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
642 #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
643 #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
644 #define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
648 #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
653 #define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
654 #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
655 #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
656 #define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
660 #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
665 #define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
666 #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
667 #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
668 #define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
672 #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
677 #define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
678 #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
679 #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
680 #define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
684 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
689 #define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
690 #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
691 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
692 #define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
696 #define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
705 #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
710 #define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
719 #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
724 #define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3)
733 #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
739 #define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3)
748 #define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3)
753 #define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3)
758 #define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0)
759 #define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1)
760 #define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2)
761 #define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3)
765 #define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
774 #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
779 #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
784 #define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
785 #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
786 #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
787 #define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
791 #define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
800 #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
805 #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
810 #define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
811 #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
812 #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
813 #define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
818 #define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
827 #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
832 #define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
841 #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
846 #define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
855 #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
860 #define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
869 #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
874 #define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
883 #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
888 #define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
897 #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
902 #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
907 #define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
908 #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
909 #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
910 #define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
914 #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
919 #define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
920 #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
921 #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
922 #define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
926 #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
931 #define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
932 #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
933 #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
934 #define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
938 #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
943 #define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
944 #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
945 #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
946 #define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
950 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
955 #define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
956 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
957 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
958 #define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
962 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
967 #define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
968 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
969 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
970 #define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
974 #define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
983 #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
988 #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
993 #define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
994 #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
995 #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
996 #define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
1000 #define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
1009 #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1014 #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1019 #define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
1020 #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1021 #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1022 #define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
1026 #define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
1035 #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1040 #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1045 #define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
1046 #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1047 #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1048 #define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
1052 #define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
1061 #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1066 #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1071 #define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
1072 #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1073 #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1074 #define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
1079 #define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
1088 #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1093 #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1098 #define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
1099 #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1100 #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1101 #define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
1105 #define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
1114 #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1119 #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1124 #define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
1125 #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1126 #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1127 #define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
1131 #define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
1140 #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1145 #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1150 #define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
1151 #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1152 #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1153 #define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
1157 #define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
1166 #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1171 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1176 #define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
1177 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1178 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1179 #define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
1183 #define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
1192 #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1197 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1202 #define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
1203 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1204 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1205 #define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
1209 #define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
1218 #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1223 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1228 #define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
1229 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1230 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1231 #define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
1236 #define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
1245 #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1250 #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1255 #define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
1256 #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1257 #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1258 #define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
1262 #define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
1271 #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1276 #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1281 #define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
1282 #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1283 #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1284 #define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
1288 #define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
1297 #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1302 #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1307 #define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
1308 #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1309 #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1310 #define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
1314 #define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
1323 #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1328 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1333 #define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
1334 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1335 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1336 #define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
1340 #define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
1349 #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1354 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1359 #define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
1360 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1361 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1362 #define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
1366 #define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
1375 #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1380 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1385 #define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
1386 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1387 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1388 #define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
1393 #define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
1402 #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1407 #define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
1416 #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1421 #define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
1430 #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1435 #define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
1444 #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1449 #define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
1458 #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1463 #define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
1472 #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1478 #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1483 #define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
1484 #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1485 #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1486 #define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
1490 #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1495 #define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
1496 #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1497 #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1498 #define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
1502 #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1507 #define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
1508 #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1509 #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1510 #define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
1514 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1519 #define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
1520 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1521 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1522 #define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
1526 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1531 #define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
1532 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1533 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1534 #define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
1538 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1543 #define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
1544 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1545 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1546 #define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
1551 #define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
1560 #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1565 #define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
1574 #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1579 #define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
1588 #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1593 #define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
1602 #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1607 #define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
1616 #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1621 #define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
1630 #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1636 #define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3)
1645 #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
1650 #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
1655 #define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0)
1656 #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
1657 #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
1658 #define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3)
1662 #define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
1671 #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1676 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1681 #define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
1682 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1683 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1684 #define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
1688 #define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3)
1697 #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
1702 #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
1707 #define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0)
1708 #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1709 #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1710 #define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3)
1714 #define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
1723 #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1728 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1733 #define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
1734 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1735 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1736 #define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
1740 #define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3)
1749 #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
1754 #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1759 #define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0)
1760 #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1761 #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1762 #define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3)
1766 #define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
1775 #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1780 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1785 #define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
1786 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1787 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1788 #define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
1793 #define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3)
1802 #define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3)
1807 #define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
1816 #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1821 #define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3)
1830 #define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3)
1835 #define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
1844 #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
1849 #define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3)
1858 #define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3)
1863 #define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
1872 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)