1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_ 8 9 /** 10 * @name custom DMA flags for channel configuration 11 * @{ 12 */ 13 /** DMA cyclic mode config on bit 5*/ 14 #define STM32_DMA_CH_CFG_MODE(val) ((val & 0x1) << 5) 15 #define STM32_DMA_MODE_NORMAL STM32_DMA_CH_CFG_MODE(0) 16 #define STM32_DMA_MODE_CYCLIC STM32_DMA_CH_CFG_MODE(1) 17 18 /** DMA transfer direction config on bits 6-7 */ 19 #define STM32_DMA_CH_CFG_DIRECTION(val) ((val & 0x3) << 6) 20 #define STM32_DMA_MEMORY_TO_MEMORY STM32_DMA_CH_CFG_DIRECTION(0) 21 #define STM32_DMA_MEMORY_TO_PERIPH STM32_DMA_CH_CFG_DIRECTION(1) 22 #define STM32_DMA_PERIPH_TO_MEMORY STM32_DMA_CH_CFG_DIRECTION(2) 23 #define STM32_DMA_PERIPH_TO_PERIPH STM32_DMA_CH_CFG_DIRECTION(3) 24 25 /** DMA Peripheral increment Address config on bit 9 */ 26 #define STM32_DMA_CH_CFG_PERIPH_ADDR_INC(val) ((val & 0x1) << 9) 27 #define STM32_DMA_PERIPH_NO_INC STM32_DMA_CH_CFG_PERIPH_ADDR_INC(0) 28 #define STM32_DMA_PERIPH_INC STM32_DMA_CH_CFG_PERIPH_ADDR_INC(1) 29 30 /** DMA Memory increment Address config on bit 10 */ 31 #define STM32_DMA_CH_CFG_MEM_ADDR_INC(val) ((val & 0x1) << 10) 32 #define STM32_DMA_MEM_NO_INC STM32_DMA_CH_CFG_MEM_ADDR_INC(0) 33 #define STM32_DMA_MEM_INC STM32_DMA_CH_CFG_MEM_ADDR_INC(1) 34 35 /** DMA Peripheral data size config on bits 11, 12 */ 36 #define STM32_DMA_CH_CFG_PERIPH_WIDTH(val) ((val & 0x3) << 11) 37 #define STM32_DMA_PERIPH_8BITS STM32_DMA_CH_CFG_PERIPH_WIDTH(0) 38 #define STM32_DMA_PERIPH_16BITS STM32_DMA_CH_CFG_PERIPH_WIDTH(1) 39 #define STM32_DMA_PERIPH_32BITS STM32_DMA_CH_CFG_PERIPH_WIDTH(2) 40 41 /** DMA Memory data size config on bits 13, 14 */ 42 #define STM32_DMA_CH_CFG_MEM_WIDTH(val) ((val & 0x3) << 13) 43 #define STM32_DMA_MEM_8BITS STM32_DMA_CH_CFG_MEM_WIDTH(0) 44 #define STM32_DMA_MEM_16BITS STM32_DMA_CH_CFG_MEM_WIDTH(1) 45 #define STM32_DMA_MEM_32BITS STM32_DMA_CH_CFG_MEM_WIDTH(2) 46 47 /** DMA Peripheral increment offset config on bit 15 */ 48 #define STM32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) 49 #define STM32_DMA_OFFSET_LINKED_BUS STM32_DMA_CH_CFG_PERIPH_INC_FIXED(0) 50 #define STM32_DMA_OFFSET_FIXED_4 STM32_DMA_CH_CFG_PERIPH_INC_FIXED(1) 51 52 /** DMA Priority config on bits 16, 17*/ 53 #define STM32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) 54 #define STM32_DMA_PRIORITY_LOW STM32_DMA_CH_CFG_PRIORITY(0) 55 #define STM32_DMA_PRIORITY_MEDIUM STM32_DMA_CH_CFG_PRIORITY(1) 56 #define STM32_DMA_PRIORITY_HIGH STM32_DMA_CH_CFG_PRIORITY(2) 57 #define STM32_DMA_PRIORITY_VERY_HIGH STM32_DMA_CH_CFG_PRIORITY(3) 58 59 /** DMA FIFO threshold feature */ 60 #define STM32_DMA_FIFO_1_4 0U 61 #define STM32_DMA_FIFO_HALF 1U 62 #define STM32_DMA_FIFO_3_4 2U 63 #define STM32_DMA_FIFO_FULL 3U 64 65 /* DMA usual combination for peripheral transfer */ 66 #define STM32_DMA_PERIPH_TX (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC) 67 #define STM32_DMA_PERIPH_RX (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC) 68 69 #define STM32_DMA_16BITS (STM32_DMA_PERIPH_16BITS | STM32_DMA_MEM_16BITS) 70 71 /** @} */ 72 73 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_ */ 74
