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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg22-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
126 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
127 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
128 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
129 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
130 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
131 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
132 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
133 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
[all …]
Dxg27-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
132 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
141 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
144 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
145 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
146 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
147 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
148 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
149 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
[all …]
Dxg21-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
112 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
119 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
120 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
121 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
122 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
123 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
124 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
127 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
[all …]
Dxg24-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
157 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
167 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
171 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
172 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
173 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
174 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
175 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
176 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
[all …]
Dxg23-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
174 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
185 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
190 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
191 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
192 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
193 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
194 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
195 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
[all …]
/Zephyr-latest/arch/arm64/core/
Dearly_mem_funcs.S4 * SPDX-License-Identifier: Apache-2.0
25 /* is dst pointer 8-bytes aligned? */
30 cmp x2, #8
39 sub x2, x2, #8
40 cmp x2, #7
45 cbz x2, 4f
48 subs x2, x2, #1
58 /* are dst and src pointers 8-bytes aligned? */
64 cmp x2, #8
69 sub x2, x2, #8
[all …]
Dswitch.S4 * SPDX-License-Identifier: Apache-2.0
8 * Thread context switching for ARM64 Cortex-A (AArch64)
11 * on ARM64 Cortex-A (AArch64)
57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
69 * depth value, and before old->switch_handle is updated (making
72 stp x0, x1, [sp, #-16]!
84 ldr x2, [x0, #_thread_offset_to_tls]
90 msr tpidr_el0, x2
112 /* arch_curr_cpu()->arch.current_stack_limit = thread->arch.stack_limit */
[all …]
Dreset.S4 * SPDX-License-Identifier: Apache-2.0
17 * Platform specific pre-C init code
19 * Note: - Stack is not yet available
20 * - x23, x24 and x25 must be preserved
136 * Get the "logic" id defined by cpu_node_list statically for voting lock self-identify.
137 * It is worth noting that this is NOT the final logic id (arch_curr_cpu()->id)
139 get_cpu_logic_id x1, x2, x3, x4 //x1: MPID, x2: logic id
145 strb w5, [x4, x2]
151 strb wzr, [x4, x2]
156 strb wzr, [x4, x2]
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dlsm6dsv16x.h4 * SPDX-License-Identifier: Apache-2.0
18 #define LSM6DSV16X_DT_FS_500DPS 0x2
26 #define LSM6DSV16X_DT_ODR_AT_7Hz5 0x2
61 #define LSM6DSV16X_DT_XL_BATCHED_AT_7Hz5 0x2
76 #define LSM6DSV16X_DT_GY_BATCHED_AT_7Hz5 0x2
91 #define LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz 0x2
97 #define LSM6DSV16X_DT_SFLP_ODR_AT_60Hz 0x2
105 #define LSM6DSV16X_DT_SFLP_FIFO_GRAVITY 0x2
/Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/
Dnative_posix.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-reserved-ranges";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 compatible = "vnd,gpio-device";
16 gpio-controller;
18 #gpio-cells = < 0x2 >;
21 gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>,
27 compatible = "vnd,gpio-device";
28 gpio-controller;
[all …]
/Zephyr-latest/doc/services/pm/images/
Ddevr-async-ops.svg1 …-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/x…
10 APP -> DEV ++: ""operation(dev)""
11 DEV -> PM ++: ""pm_device_runtime_get(dev)""
12 PM -> PM: Increase usage
14 PM -> DEV ++: ""PM_DEVICE_ACTION_RESUME""
21 DEV -> PM ++: ""pm_device_runtime_put_async(dev)""
22 PM -> PM: Decrease usage
24 PM -> PM: Schedule suspend
32 WQ -> DEV ++: ""PM_DEVICE_ACTION_SUSPEND""
188 APP -> DEV ++: ""operation(dev)""
[all …]
Ddevr-sync-ops.svg1 …-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/x…
9 APP -> DEV ++: ""operation(dev)""
10 DEV -> PM ++: ""pm_device_runtime_get(dev)""
11 PM -> PM: Increase usage
13 PM -> DEV ++: ""PM_DEVICE_ACTION_RESUME""
20 DEV -> PM ++: ""pm_device_runtime_put(dev)""
21 PM -> PM: Decrease usage
23 PM -> DEV ++: ""PM_DEVICE_ACTION_SUSPEND""
181 APP -> DEV ++: ""operation(dev)""
182 DEV -> PM ++: ""pm_device_runtime_get(dev)""
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_nxp_fs26.h4 * SPDX-License-Identifier: Apache-2.0
12 /* Main or Fail-safe register selection (M/FS) */
32 /* Interrupt notification from the Fail-Safe domain */
72 #define FS26_M_STATUS (0x2)
133 #define VMON_PRE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_OV_FS_REACTION_SHIFT)
140 #define VMON_PRE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_PRE_UV_FS_REACTION_SHIFT)
147 #define VMON_CORE_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_OV_FS_REACTION_SHIFT)
154 #define VMON_CORE_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_CORE_UV_FS_REACTION_SHIFT)
161 #define VMON_LDO1_OV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_OV_FS_REACTION_SHIFT)
168 #define VMON_LDO1_UV_FS_REACTION_RSTB_FS0B (0x2 << VMON_LDO1_UV_FS_REACTION_SHIFT)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp-pinctrl-common.h4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/dt-util.h>
47 #define ESP32_PULL_UP 0x2
52 #define ESP32_OPEN_DRAIN 0x2
59 #define ESP32_PIN_OUT_LOW 0x2
66 #define ESP32_PIN_IN_EN 0x2
/Zephyr-latest/include/zephyr/posix/sys/
Dmman.h4 * SPDX-License-Identifier: Apache-2.0
15 #define PROT_WRITE 0x2
19 #define MAP_PRIVATE 0x2
27 #define MS_INVALIDATE 0x2
29 #define MAP_FAILED ((void *)-1)
/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
20 - bit 10: Memory address increase
[all …]
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
28 0x2: PERIPH to MEM
30 -bit 9 : Peripheral Increment Address
33 -bit 10 : Memory Increment Address
[all …]
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
[all …]
Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
22 0x2: STM32_DMA_PERIPH_TO_MEMORY: PERIPH to MEM
24 -bit 9 : Peripheral Increment Address
[all …]
Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
18 0x2: PERIPH to MEM
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
28 0x1: Half-word (16 bits)
[all …]
/Zephyr-latest/tests/drivers/stepper/drv8424/emul/boards/
Dnative_sim.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
14 dir-gpios = <&gpio1 0 0>; /* D3 */
15 step-gpios = <&gpio1 1 0>; /* D4 */
16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/Zephyr-latest/tests/drivers/stepper/drv8424/api/boards/
Dnative_sim.overlay3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/gpio/gpio.h>
14 dir-gpios = <&gpio1 0 0>; /* D3 */
15 step-gpios = <&gpio1 1 0>; /* D4 */
16 sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
17 en-gpios = <&gpio2 1 0>; /* 5 */
18 m0-gpios = <&gpio3 0 0>;
19 m1-gpios = <&gpio3 1 0>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-alts-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 npcx-alts-map {
9 compatible = "nuvoton,npcx-pinctrl-conf";
16 alt0_gpio_no_spip: alt03-inv {
19 alt0_gpio_no_fpip: alt07-inv {
29 alts = <&scfg 0x01 0x2 0>;
34 alt1_no_pwrgd: alt14-inv {
43 alt1_no_lpc_espi: alt17-inv {
55 alts = <&scfg 0x02 0x2 0>;
78 alts = <&scfg 0x03 0x2 0>;
[all …]
/Zephyr-latest/include/zephyr/drivers/sensor/
Dwsen_hids_2525020210002.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Extended public API for WSEN-HIDS-2525020210002 Sensor
30 hids_2525020210002_precision_High = 0x2
36 hids_2525020210002_heater_On_200mW_100ms = 0x2,
/Zephyr-latest/dts/arm/
Dcortex_r8_virt.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-r8f";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
[all …]

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