Lines Matching +full:x2 +full:-
4 * SPDX-License-Identifier: Apache-2.0
8 * Thread context switching for ARM64 Cortex-A (AArch64)
11 * on ARM64 Cortex-A (AArch64)
57 lsr x2, x4, #TPIDRROEL0_EXC_SHIFT
63 orr x4, x4, x2, lsl #TPIDRROEL0_EXC_SHIFT
69 * depth value, and before old->switch_handle is updated (making
72 stp x0, x1, [sp, #-16]!
84 ldr x2, [x0, #_thread_offset_to_tls]
90 msr tpidr_el0, x2
112 /* arch_curr_cpu()->arch.current_stack_limit = thread->arch.stack_limit */
114 ldr x2, [x0, #_thread_offset_to_stack_limit]
115 str x2, [x4, #_cpu_offset_to_current_stack_limit]
119 str lr, [sp, #-16]!
125 str lr, [sp, #-16]!
137 * - Cooperative context switching
138 * - IRQ offloading
148 cmp x1, #0x07 /*Access to SIMD or floating-point */
182 /* ++_current_cpu->nested to be checked by arch_is_in_isr() */
183 get_cpu x2
184 ldr w3, [x2, #___cpu_t_nested_OFFSET]
186 str w4, [x2, #___cpu_t_nested_OFFSET]
190 ldr x3, [x2, #___cpu_t_irq_stack_OFFSET]
193 str x4, [sp, #-16]!
197 str x3, [x2, #_cpu_offset_to_current_stack_limit]