Lines Matching +full:x2 +full:-
3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
157 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
167 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
171 #define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
172 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
173 #define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
174 #define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
175 #define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
176 #define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
177 #define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
178 #define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
179 #define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8)
180 #define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9)
183 #define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
190 #define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2)
200 #define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2)
204 #define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0)
205 #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
206 #define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2)
207 #define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3)
208 #define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4)
209 #define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5)
210 #define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6)
211 #define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7)
212 #define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8)
213 #define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9)
216 #define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2)
221 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
222 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
223 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
224 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
225 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
226 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
227 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
228 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
229 #define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8)
230 #define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9)
233 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
237 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
238 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
239 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
240 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
241 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
242 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
243 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
244 #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
245 #define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8)
246 #define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9)
249 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
255 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
265 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
269 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
270 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
271 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
272 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
273 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
274 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
275 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
276 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
277 #define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8)
278 #define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9)
281 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
288 #define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2)
298 #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
304 #define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
314 #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
320 #define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2)
330 #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
336 #define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
346 #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
352 #define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2)
362 #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
368 #define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
378 #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
385 #define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2)
395 #define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2)
399 #define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0)
400 #define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1)
401 #define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2)
402 #define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3)
403 #define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4)
404 #define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5)
405 #define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6)
406 #define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7)
407 #define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8)
408 #define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9)
411 #define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2)
417 #define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
427 #define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
431 #define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
432 #define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
433 #define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
434 #define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
435 #define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
436 #define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
437 #define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
438 #define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
439 #define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8)
440 #define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9)
443 #define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
449 #define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2)
459 #define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2)
463 #define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0)
464 #define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1)
465 #define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2)
466 #define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3)
467 #define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4)
468 #define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5)
469 #define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6)
470 #define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7)
471 #define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8)
472 #define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9)
475 #define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2)
481 #define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
491 #define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
495 #define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
496 #define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
497 #define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
498 #define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
499 #define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
500 #define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
501 #define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
502 #define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
503 #define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8)
504 #define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9)
507 #define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
513 #define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2)
523 #define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2)
527 #define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0)
528 #define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1)
529 #define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2)
530 #define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3)
531 #define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4)
532 #define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5)
533 #define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6)
534 #define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7)
535 #define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8)
536 #define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9)
539 #define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2)
545 #define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
555 #define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
559 #define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
560 #define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
561 #define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
562 #define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
563 #define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
564 #define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
565 #define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
566 #define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
567 #define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8)
568 #define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9)
571 #define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
576 #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
577 #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
578 #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
579 #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
580 #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
581 #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
582 #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
583 #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
584 #define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8)
585 #define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9)
588 #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
592 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
593 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
594 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
595 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
596 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
597 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
598 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
599 #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
600 #define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8)
601 #define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9)
604 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
608 #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
609 #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
610 #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
611 #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
612 #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
613 #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
614 #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
615 #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
616 #define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8)
617 #define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9)
620 #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
627 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
637 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
641 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
642 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
643 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
644 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
645 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
646 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
647 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
648 #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
649 #define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8)
650 #define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9)
653 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
659 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
669 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
673 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
674 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
675 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
676 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
677 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
678 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
679 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
680 #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
681 #define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8)
682 #define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9)
685 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
690 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
691 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
692 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
693 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
694 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
695 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
696 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
697 #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
698 #define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8)
699 #define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9)
702 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
706 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
707 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
708 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
709 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
710 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
711 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
712 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
713 #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
714 #define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8)
715 #define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9)
718 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
725 #define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2)
735 #define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2)
739 #define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0)
740 #define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1)
741 #define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2)
742 #define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3)
743 #define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4)
744 #define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5)
745 #define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6)
746 #define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7)
747 #define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8)
748 #define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9)
751 #define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2)
757 #define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2)
767 #define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2)
771 #define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0)
772 #define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1)
773 #define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2)
774 #define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3)
775 #define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4)
776 #define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5)
777 #define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6)
778 #define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7)
779 #define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8)
780 #define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9)
783 #define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2)
789 #define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2)
799 #define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2)
803 #define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0)
804 #define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1)
805 #define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2)
806 #define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3)
807 #define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4)
808 #define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5)
809 #define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6)
810 #define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7)
811 #define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8)
812 #define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9)
815 #define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2)
821 #define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2)
831 #define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2)
835 #define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0)
836 #define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1)
837 #define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2)
838 #define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3)
839 #define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4)
840 #define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5)
841 #define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6)
842 #define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7)
843 #define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8)
844 #define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9)
847 #define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2)
853 #define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2)
863 #define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2)
867 #define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0)
868 #define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1)
869 #define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2)
870 #define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3)
871 #define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4)
872 #define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5)
873 #define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6)
874 #define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7)
875 #define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8)
876 #define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9)
879 #define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2)
885 #define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2)
895 #define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2)
899 #define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0)
900 #define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1)
901 #define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2)
902 #define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3)
903 #define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4)
904 #define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5)
905 #define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6)
906 #define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7)
907 #define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8)
908 #define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9)
911 #define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2)
917 #define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2)
927 #define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2)
931 #define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0)
932 #define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1)
933 #define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2)
934 #define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3)
935 #define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4)
936 #define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5)
937 #define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6)
938 #define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7)
939 #define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8)
940 #define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9)
943 #define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2)
949 #define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2)
959 #define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2)
963 #define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0)
964 #define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1)
965 #define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2)
966 #define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3)
967 #define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4)
968 #define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5)
969 #define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6)
970 #define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7)
971 #define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8)
972 #define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9)
975 #define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2)
981 #define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2)
991 #define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2)
997 #define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2)
1007 #define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2)
1013 #define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2)
1023 #define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2)
1029 #define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2)
1039 #define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2)
1045 #define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2)
1055 #define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2)
1061 #define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2)
1071 #define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2)
1078 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
1088 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
1094 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
1104 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
1111 #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
1121 #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
1125 #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
1126 #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
1127 #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
1128 #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
1129 #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
1130 #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
1131 #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
1132 #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
1133 #define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8)
1134 #define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9)
1137 #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
1143 #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
1153 #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
1157 #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
1158 #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
1159 #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
1160 #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
1161 #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
1162 #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
1163 #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
1164 #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
1165 #define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8)
1166 #define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9)
1169 #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
1173 #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
1174 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
1175 #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
1176 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
1177 #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
1178 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
1179 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
1180 #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
1181 #define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8)
1182 #define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9)
1185 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
1189 #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
1190 #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
1191 #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
1192 #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
1193 #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
1194 #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
1195 #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
1196 #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
1197 #define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8)
1198 #define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9)
1201 #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
1205 #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
1206 #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
1207 #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
1208 #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
1209 #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
1210 #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
1211 #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
1212 #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
1213 #define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8)
1214 #define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9)
1217 #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
1221 #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
1222 #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
1223 #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
1224 #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
1225 #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
1226 #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
1227 #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
1228 #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
1229 #define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8)
1230 #define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9)
1233 #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
1237 #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
1238 #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
1239 #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
1240 #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
1241 #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
1242 #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
1243 #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
1244 #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
1245 #define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8)
1246 #define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9)
1249 #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
1253 #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
1254 #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
1255 #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
1256 #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
1257 #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
1258 #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
1259 #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
1260 #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
1261 #define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8)
1262 #define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9)
1265 #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
1269 #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
1270 #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
1271 #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
1272 #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
1273 #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
1274 #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
1275 #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
1276 #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
1277 #define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8)
1278 #define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9)
1281 #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
1285 #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
1286 #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
1287 #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
1288 #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
1289 #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
1290 #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
1291 #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
1292 #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
1293 #define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8)
1294 #define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9)
1297 #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
1301 #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
1302 #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
1303 #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
1304 #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
1305 #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
1306 #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
1307 #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
1308 #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
1309 #define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8)
1310 #define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9)
1313 #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
1317 #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
1318 #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
1319 #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
1320 #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
1321 #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
1322 #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
1323 #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
1324 #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
1325 #define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8)
1326 #define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9)
1329 #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
1333 #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
1334 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
1335 #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
1336 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
1337 #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
1338 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
1339 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
1340 #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
1341 #define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8)
1342 #define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9)
1345 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
1351 #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
1361 #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
1367 #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
1377 #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
1383 #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
1393 #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
1400 #define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2)
1410 #define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2)
1416 #define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2)
1426 #define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2)
1433 #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
1443 #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
1449 #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
1459 #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
1465 #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
1475 #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
1481 #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
1491 #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
1497 #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
1507 #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
1513 #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
1523 #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
1527 #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
1528 #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
1529 #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
1530 #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
1531 #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
1532 #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
1533 #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
1534 #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
1535 #define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8)
1536 #define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9)
1539 #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
1543 #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
1544 #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
1545 #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
1546 #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
1547 #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
1548 #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
1549 #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
1550 #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
1551 #define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8)
1552 #define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9)
1555 #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
1559 #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
1560 #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
1561 #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
1562 #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
1563 #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
1564 #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
1565 #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
1566 #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
1567 #define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8)
1568 #define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9)
1571 #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
1575 #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
1576 #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
1577 #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
1578 #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
1579 #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
1580 #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
1581 #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
1582 #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
1583 #define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8)
1584 #define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9)
1587 #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
1591 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
1592 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
1593 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
1594 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
1595 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
1596 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
1597 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
1598 #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
1599 #define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8)
1600 #define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9)
1603 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
1607 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
1608 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
1609 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
1610 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
1611 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
1612 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
1613 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
1614 #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
1615 #define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8)
1616 #define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9)
1619 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
1625 #define PRS0_ASYNCH12_PA2 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x2)
1635 #define PRS0_ASYNCH12_PB2 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x2)
1641 #define PRS0_ASYNCH13_PA2 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x2)
1651 #define PRS0_ASYNCH13_PB2 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x2)
1657 #define PRS0_ASYNCH14_PA2 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x2)
1667 #define PRS0_ASYNCH14_PB2 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x2)
1673 #define PRS0_ASYNCH15_PA2 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x2)
1683 #define PRS0_ASYNCH15_PB2 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x2)
1689 #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
1699 #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
1703 #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
1704 #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
1705 #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
1706 #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
1707 #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
1708 #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
1709 #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
1710 #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
1711 #define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8)
1712 #define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9)
1715 #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
1721 #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
1731 #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1735 #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
1736 #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1737 #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
1738 #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
1739 #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
1740 #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
1741 #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
1742 #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
1743 #define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8)
1744 #define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9)
1747 #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
1753 #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
1763 #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1767 #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
1768 #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1769 #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
1770 #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
1771 #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
1772 #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
1773 #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
1774 #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
1775 #define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8)
1776 #define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9)
1779 #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
1785 #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
1795 #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1799 #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
1800 #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1801 #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
1802 #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
1803 #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
1804 #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
1805 #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
1806 #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
1807 #define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8)
1808 #define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9)
1811 #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
1818 #define HFXO0_BUFOUTREQINASYNC_PA2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x2)
1828 #define HFXO0_BUFOUTREQINASYNC_PB2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x2)
1835 #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1845 #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1849 #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1850 #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1851 #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1852 #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1853 #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1854 #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1855 #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1856 #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1857 #define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8)
1858 #define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9)
1861 #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1867 #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1877 #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1881 #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1882 #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1883 #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1884 #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1885 #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1886 #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1887 #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1888 #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1889 #define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8)
1890 #define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9)
1893 #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1899 #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1909 #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1913 #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1914 #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1915 #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1916 #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1917 #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1918 #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1919 #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1920 #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1921 #define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8)
1922 #define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9)
1925 #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1931 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1941 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1945 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1946 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1947 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1948 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1949 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1950 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1951 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1952 #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1953 #define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8)
1954 #define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9)
1957 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1963 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1973 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1977 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1978 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1979 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1980 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1981 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1982 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1983 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1984 #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1985 #define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8)
1986 #define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9)
1989 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1995 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
2005 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
2009 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
2010 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
2011 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
2012 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
2013 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
2014 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
2015 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
2016 #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
2017 #define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8)
2018 #define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9)
2021 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
2028 #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
2038 #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
2042 #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
2043 #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
2044 #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
2045 #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
2046 #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
2047 #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
2048 #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
2049 #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
2050 #define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8)
2051 #define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9)
2054 #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
2060 #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
2070 #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
2074 #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
2075 #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
2076 #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
2077 #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
2078 #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
2079 #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
2080 #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
2081 #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
2082 #define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8)
2083 #define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9)
2086 #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
2092 #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
2102 #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
2106 #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
2107 #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
2108 #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
2109 #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
2110 #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
2111 #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
2112 #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
2113 #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
2114 #define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8)
2115 #define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9)
2118 #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
2124 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
2134 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
2138 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
2139 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
2140 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
2141 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
2142 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
2143 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
2144 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
2145 #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
2146 #define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8)
2147 #define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9)
2150 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
2156 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
2166 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
2170 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
2171 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
2172 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
2173 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
2174 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
2175 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
2176 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
2177 #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
2178 #define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8)
2179 #define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9)
2182 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
2188 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
2198 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
2202 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
2203 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
2204 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
2205 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
2206 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
2207 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
2208 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
2209 #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
2210 #define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8)
2211 #define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9)
2214 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
2221 #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
2231 #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
2237 #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
2247 #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
2253 #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
2263 #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
2269 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
2279 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
2285 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
2295 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
2301 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
2311 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
2316 #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
2317 #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
2318 #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
2319 #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
2320 #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
2321 #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
2322 #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
2323 #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
2324 #define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8)
2325 #define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9)
2328 #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
2332 #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
2333 #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
2334 #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
2335 #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
2336 #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
2337 #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
2338 #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
2339 #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
2340 #define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8)
2341 #define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9)
2344 #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
2348 #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
2349 #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
2350 #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
2351 #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
2352 #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
2353 #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
2354 #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
2355 #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
2356 #define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8)
2357 #define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9)
2360 #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
2364 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
2365 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
2366 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
2367 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
2368 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
2369 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
2370 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
2371 #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
2372 #define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8)
2373 #define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9)
2376 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
2380 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
2381 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
2382 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
2383 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
2384 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
2385 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
2386 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
2387 #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
2388 #define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8)
2389 #define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9)
2392 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
2396 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
2397 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
2398 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
2399 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
2400 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
2401 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
2402 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
2403 #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
2404 #define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8)
2405 #define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9)
2408 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
2415 #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
2425 #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
2431 #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
2441 #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
2447 #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
2457 #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
2463 #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
2473 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
2479 #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
2489 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
2495 #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
2505 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
2512 #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
2522 #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
2526 #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
2527 #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
2528 #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
2529 #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
2530 #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
2531 #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
2532 #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
2533 #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
2534 #define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8)
2535 #define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9)
2538 #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
2544 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
2554 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
2558 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
2559 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
2560 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
2561 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
2562 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
2563 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
2564 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
2565 #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
2566 #define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8)
2567 #define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9)
2570 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
2576 #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
2586 #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
2590 #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
2591 #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
2592 #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
2593 #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
2594 #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
2595 #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
2596 #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
2597 #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
2598 #define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8)
2599 #define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9)
2602 #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
2608 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
2618 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
2622 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
2623 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
2624 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
2625 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
2626 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
2627 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
2628 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
2629 #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
2630 #define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8)
2631 #define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9)
2634 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
2640 #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
2650 #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
2654 #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
2655 #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
2656 #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
2657 #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
2658 #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
2659 #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
2660 #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
2661 #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
2662 #define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8)
2663 #define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9)
2666 #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
2672 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
2682 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
2686 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
2687 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
2688 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
2689 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
2690 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
2691 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
2692 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
2693 #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
2694 #define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8)
2695 #define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9)
2698 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)