Lines Matching +full:x2 +full:-
3 * SPDX-License-Identifier: Apache-2.0
14 #include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
126 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
127 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
128 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
129 #define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
130 #define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
131 #define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
132 #define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
133 #define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
136 #define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
138 #define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
139 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
140 #define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
141 #define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
142 #define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
143 #define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
144 #define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
145 #define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
148 #define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
152 #define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
161 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
164 #define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
165 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
166 #define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
167 #define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
168 #define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
169 #define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
170 #define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
171 #define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
174 #define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
177 #define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0)
178 #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
179 #define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2)
180 #define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3)
181 #define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4)
182 #define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5)
183 #define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6)
184 #define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7)
187 #define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2)
189 #define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
190 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
191 #define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
192 #define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
193 #define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
194 #define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
195 #define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
196 #define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
199 #define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
201 #define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0)
202 #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
203 #define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2)
204 #define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3)
205 #define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4)
206 #define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5)
207 #define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6)
208 #define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7)
211 #define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2)
216 #define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
225 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
228 #define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
229 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
230 #define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
231 #define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
232 #define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
233 #define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
234 #define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
235 #define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
238 #define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
242 #define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
251 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
254 #define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
255 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
256 #define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
257 #define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
258 #define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
259 #define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
260 #define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
261 #define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
264 #define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
267 #define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
268 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
269 #define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
270 #define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
271 #define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
272 #define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
273 #define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
274 #define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
277 #define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
279 #define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
280 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
281 #define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
282 #define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
283 #define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
284 #define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
285 #define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
286 #define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
289 #define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
294 #define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
303 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
308 #define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
317 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
323 #define EUART0_RTS_PA2 SILABS_DBUS_EUART0_RTS(0x0, 0x2)
332 #define EUART0_RTS_PB2 SILABS_DBUS_EUART0_RTS(0x1, 0x2)
335 #define EUART0_RTS_PC0 SILABS_DBUS_EUART0_RTS(0x2, 0x0)
336 #define EUART0_RTS_PC1 SILABS_DBUS_EUART0_RTS(0x2, 0x1)
337 #define EUART0_RTS_PC2 SILABS_DBUS_EUART0_RTS(0x2, 0x2)
338 #define EUART0_RTS_PC3 SILABS_DBUS_EUART0_RTS(0x2, 0x3)
339 #define EUART0_RTS_PC4 SILABS_DBUS_EUART0_RTS(0x2, 0x4)
340 #define EUART0_RTS_PC5 SILABS_DBUS_EUART0_RTS(0x2, 0x5)
341 #define EUART0_RTS_PC6 SILABS_DBUS_EUART0_RTS(0x2, 0x6)
342 #define EUART0_RTS_PC7 SILABS_DBUS_EUART0_RTS(0x2, 0x7)
345 #define EUART0_RTS_PD2 SILABS_DBUS_EUART0_RTS(0x3, 0x2)
349 #define EUART0_TX_PA2 SILABS_DBUS_EUART0_TX(0x0, 0x2)
358 #define EUART0_TX_PB2 SILABS_DBUS_EUART0_TX(0x1, 0x2)
361 #define EUART0_TX_PC0 SILABS_DBUS_EUART0_TX(0x2, 0x0)
362 #define EUART0_TX_PC1 SILABS_DBUS_EUART0_TX(0x2, 0x1)
363 #define EUART0_TX_PC2 SILABS_DBUS_EUART0_TX(0x2, 0x2)
364 #define EUART0_TX_PC3 SILABS_DBUS_EUART0_TX(0x2, 0x3)
365 #define EUART0_TX_PC4 SILABS_DBUS_EUART0_TX(0x2, 0x4)
366 #define EUART0_TX_PC5 SILABS_DBUS_EUART0_TX(0x2, 0x5)
367 #define EUART0_TX_PC6 SILABS_DBUS_EUART0_TX(0x2, 0x6)
368 #define EUART0_TX_PC7 SILABS_DBUS_EUART0_TX(0x2, 0x7)
371 #define EUART0_TX_PD2 SILABS_DBUS_EUART0_TX(0x3, 0x2)
375 #define EUART0_CTS_PA2 SILABS_DBUS_EUART0_CTS(0x0, 0x2)
384 #define EUART0_CTS_PB2 SILABS_DBUS_EUART0_CTS(0x1, 0x2)
387 #define EUART0_CTS_PC0 SILABS_DBUS_EUART0_CTS(0x2, 0x0)
388 #define EUART0_CTS_PC1 SILABS_DBUS_EUART0_CTS(0x2, 0x1)
389 #define EUART0_CTS_PC2 SILABS_DBUS_EUART0_CTS(0x2, 0x2)
390 #define EUART0_CTS_PC3 SILABS_DBUS_EUART0_CTS(0x2, 0x3)
391 #define EUART0_CTS_PC4 SILABS_DBUS_EUART0_CTS(0x2, 0x4)
392 #define EUART0_CTS_PC5 SILABS_DBUS_EUART0_CTS(0x2, 0x5)
393 #define EUART0_CTS_PC6 SILABS_DBUS_EUART0_CTS(0x2, 0x6)
394 #define EUART0_CTS_PC7 SILABS_DBUS_EUART0_CTS(0x2, 0x7)
397 #define EUART0_CTS_PD2 SILABS_DBUS_EUART0_CTS(0x3, 0x2)
401 #define EUART0_RX_PA2 SILABS_DBUS_EUART0_RX(0x0, 0x2)
410 #define EUART0_RX_PB2 SILABS_DBUS_EUART0_RX(0x1, 0x2)
413 #define EUART0_RX_PC0 SILABS_DBUS_EUART0_RX(0x2, 0x0)
414 #define EUART0_RX_PC1 SILABS_DBUS_EUART0_RX(0x2, 0x1)
415 #define EUART0_RX_PC2 SILABS_DBUS_EUART0_RX(0x2, 0x2)
416 #define EUART0_RX_PC3 SILABS_DBUS_EUART0_RX(0x2, 0x3)
417 #define EUART0_RX_PC4 SILABS_DBUS_EUART0_RX(0x2, 0x4)
418 #define EUART0_RX_PC5 SILABS_DBUS_EUART0_RX(0x2, 0x5)
419 #define EUART0_RX_PC6 SILABS_DBUS_EUART0_RX(0x2, 0x6)
420 #define EUART0_RX_PC7 SILABS_DBUS_EUART0_RX(0x2, 0x7)
423 #define EUART0_RX_PD2 SILABS_DBUS_EUART0_RX(0x3, 0x2)
428 #define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
437 #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
440 #define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
441 #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
442 #define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
443 #define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
444 #define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
445 #define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
446 #define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
447 #define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
450 #define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
454 #define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
463 #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
466 #define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
467 #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
468 #define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
469 #define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
470 #define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
471 #define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
472 #define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
473 #define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
476 #define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
478 #define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
479 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
480 #define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
481 #define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
482 #define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
483 #define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
484 #define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
485 #define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
488 #define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
490 #define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
491 #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
492 #define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
493 #define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
494 #define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
495 #define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
496 #define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
497 #define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
500 #define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
502 #define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
503 #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
504 #define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
505 #define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
506 #define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
507 #define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
508 #define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
509 #define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
512 #define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
514 #define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
515 #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
516 #define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
517 #define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
518 #define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
519 #define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
520 #define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
521 #define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
524 #define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
526 #define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
527 #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
528 #define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
529 #define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
530 #define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
531 #define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
532 #define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
533 #define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
536 #define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
538 #define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
539 #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
540 #define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
541 #define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
542 #define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
543 #define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
544 #define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
545 #define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
548 #define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
550 #define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
551 #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
552 #define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
553 #define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
554 #define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
555 #define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
556 #define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
557 #define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
560 #define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
562 #define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
563 #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
564 #define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
565 #define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
566 #define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
567 #define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
568 #define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
569 #define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
572 #define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
574 #define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
575 #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
576 #define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
577 #define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
578 #define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
579 #define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
580 #define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
581 #define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
584 #define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
586 #define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
587 #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
588 #define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
589 #define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
590 #define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
591 #define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
592 #define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
593 #define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
596 #define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
598 #define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
599 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
600 #define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
601 #define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
602 #define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
603 #define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
604 #define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
605 #define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
608 #define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
612 #define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
621 #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
626 #define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
635 #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
640 #define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2)
649 #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
655 #define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2)
664 #define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2)
667 #define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0)
668 #define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1)
669 #define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2)
670 #define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3)
671 #define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4)
672 #define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5)
673 #define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6)
674 #define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7)
677 #define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2)
681 #define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
690 #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
693 #define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
694 #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
695 #define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
696 #define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
697 #define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
698 #define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
699 #define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
700 #define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
703 #define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
707 #define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
716 #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
719 #define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
720 #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
721 #define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
722 #define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
723 #define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
724 #define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
725 #define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
726 #define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
729 #define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
734 #define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
743 #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
748 #define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
757 #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
762 #define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
771 #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
776 #define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
785 #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
790 #define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
799 #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
804 #define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
813 #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
816 #define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
817 #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
818 #define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
819 #define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
820 #define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
821 #define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
822 #define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
823 #define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
826 #define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
828 #define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
829 #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
830 #define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
831 #define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
832 #define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
833 #define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
834 #define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
835 #define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
838 #define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
840 #define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
841 #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
842 #define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
843 #define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
844 #define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
845 #define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
846 #define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
847 #define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
850 #define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
852 #define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
853 #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
854 #define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
855 #define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
856 #define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
857 #define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
858 #define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
859 #define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
862 #define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
864 #define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
865 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
866 #define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
867 #define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
868 #define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
869 #define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
870 #define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
871 #define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
874 #define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
876 #define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
877 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
878 #define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
879 #define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
880 #define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
881 #define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
882 #define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
883 #define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
886 #define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
890 #define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
899 #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
902 #define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
903 #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
904 #define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
905 #define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
906 #define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
907 #define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
908 #define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
909 #define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
912 #define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
916 #define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
925 #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
928 #define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
929 #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
930 #define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
931 #define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
932 #define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
933 #define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
934 #define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
935 #define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
938 #define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
942 #define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
951 #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
954 #define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
955 #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
956 #define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
957 #define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
958 #define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
959 #define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
960 #define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
961 #define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
964 #define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
968 #define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
977 #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
980 #define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
981 #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
982 #define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
983 #define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
984 #define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
985 #define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
986 #define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
987 #define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
990 #define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
995 #define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
1004 #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1007 #define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
1008 #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1009 #define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
1010 #define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
1011 #define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
1012 #define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
1013 #define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
1014 #define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
1017 #define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
1021 #define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
1030 #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1033 #define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
1034 #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1035 #define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
1036 #define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
1037 #define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
1038 #define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
1039 #define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
1040 #define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
1043 #define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
1047 #define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
1056 #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1059 #define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
1060 #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1061 #define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
1062 #define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
1063 #define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
1064 #define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
1065 #define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
1066 #define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
1069 #define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
1073 #define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
1082 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1085 #define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
1086 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1087 #define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
1088 #define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
1089 #define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
1090 #define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
1091 #define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
1092 #define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
1095 #define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
1099 #define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
1108 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1111 #define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
1112 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1113 #define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
1114 #define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
1115 #define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
1116 #define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
1117 #define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
1118 #define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
1121 #define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
1125 #define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
1134 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1137 #define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
1138 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1139 #define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
1140 #define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
1141 #define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
1142 #define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
1143 #define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
1144 #define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
1147 #define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
1152 #define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
1161 #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1164 #define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
1165 #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1166 #define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
1167 #define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
1168 #define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
1169 #define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
1170 #define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
1171 #define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
1174 #define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
1178 #define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
1187 #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1190 #define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
1191 #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1192 #define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
1193 #define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
1194 #define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
1195 #define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
1196 #define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
1197 #define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
1200 #define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
1204 #define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
1213 #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1216 #define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
1217 #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1218 #define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
1219 #define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
1220 #define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
1221 #define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
1222 #define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
1223 #define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
1226 #define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
1230 #define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
1239 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1242 #define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
1243 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1244 #define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
1245 #define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
1246 #define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
1247 #define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
1248 #define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
1249 #define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
1252 #define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
1256 #define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
1265 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1268 #define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
1269 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1270 #define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
1271 #define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
1272 #define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
1273 #define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
1274 #define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
1275 #define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
1278 #define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
1282 #define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
1291 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1294 #define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
1295 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1296 #define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
1297 #define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
1298 #define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
1299 #define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
1300 #define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
1301 #define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
1304 #define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
1309 #define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
1318 #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1323 #define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
1332 #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1337 #define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
1346 #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1351 #define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
1360 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1365 #define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
1374 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1379 #define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
1388 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1392 #define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
1393 #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1394 #define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
1395 #define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
1396 #define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
1397 #define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
1398 #define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
1399 #define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
1402 #define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
1404 #define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
1405 #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1406 #define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
1407 #define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
1408 #define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
1409 #define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
1410 #define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
1411 #define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
1414 #define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
1416 #define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
1417 #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1418 #define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
1419 #define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
1420 #define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
1421 #define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
1422 #define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
1423 #define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
1426 #define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
1428 #define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
1429 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1430 #define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
1431 #define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
1432 #define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
1433 #define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
1434 #define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
1435 #define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
1438 #define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
1440 #define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
1441 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1442 #define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
1443 #define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
1444 #define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
1445 #define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
1446 #define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
1447 #define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
1450 #define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
1452 #define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
1453 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1454 #define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
1455 #define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
1456 #define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
1457 #define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
1458 #define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
1459 #define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
1462 #define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
1467 #define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
1476 #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1481 #define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
1490 #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1495 #define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
1504 #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1509 #define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
1518 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1523 #define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
1532 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1537 #define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
1546 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1552 #define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2)
1561 #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
1564 #define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0)
1565 #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
1566 #define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2)
1567 #define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3)
1568 #define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4)
1569 #define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5)
1570 #define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6)
1571 #define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7)
1574 #define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2)
1578 #define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
1587 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1590 #define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
1591 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1592 #define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
1593 #define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
1594 #define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
1595 #define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
1596 #define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
1597 #define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
1600 #define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
1604 #define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2)
1613 #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
1616 #define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0)
1617 #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
1618 #define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2)
1619 #define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3)
1620 #define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4)
1621 #define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5)
1622 #define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6)
1623 #define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7)
1626 #define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2)
1630 #define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
1639 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1642 #define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
1643 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1644 #define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
1645 #define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
1646 #define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
1647 #define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
1648 #define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
1649 #define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
1652 #define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
1656 #define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2)
1665 #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
1668 #define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0)
1669 #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1670 #define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2)
1671 #define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3)
1672 #define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4)
1673 #define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5)
1674 #define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6)
1675 #define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7)
1678 #define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2)
1682 #define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
1691 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1694 #define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
1695 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1696 #define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
1697 #define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
1698 #define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
1699 #define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
1700 #define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
1701 #define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
1704 #define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
1709 #define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2)
1718 #define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2)
1723 #define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
1732 #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1737 #define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2)
1746 #define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2)
1751 #define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
1760 #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
1765 #define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2)
1774 #define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2)
1779 #define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
1788 #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)