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/Zephyr-latest/dts/bindings/clock/
Dintel,adsp-shim-clkctl.yaml9 adsp-clkctl-clk-wovcro:
12 Index of WOVCRO clock encoding in the encoding array (if wovcro-supported is true).
45 wovcro-supported:
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_shim.h105 #define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
106 #define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */
/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dadsp_clk.h59 #define ADSP_CPU_CLOCK_FREQ_WOVCRO ADSP_CPU_CLOCK_FREQ(wovcro)
/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_cavs25_tgph.dtsi77 adsp-clkctl-clk-wovcro = <0>;
84 wovcro-supported;
Dintel_adsp_cavs25.dtsi92 adsp-clkctl-clk-wovcro = <0>;
99 wovcro-supported;
Dintel_adsp_ace20_lnl.dtsi98 adsp-clkctl-clk-wovcro = <0>;
104 wovcro-supported;
Dintel_adsp_ace15_mtpm.dtsi84 adsp-clkctl-clk-wovcro = <0>;
90 wovcro-supported;
Dintel_adsp_ace30.dtsi98 adsp-clkctl-clk-wovcro = <0>;
104 wovcro-supported;
Dintel_adsp_ace30_ptl.dtsi98 adsp-clkctl-clk-wovcro = <0>;
104 wovcro-supported;
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Dadsp_shim.h103 #define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Dadsp_shim.h154 #define ACE_CLKCTL_WOVCRO BIT(21) /* Request WOVCRO clock */
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Dadsp_shim.h154 #define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst1239 * :dtcompatible:`intel,adsp-shim-clkctl`: new ``wovcro-supported`` property.