1/*
2 * Copyright (c) 2019,2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/intel/intel_adsp_cavs.dtsi>
8#include <mem.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "cdns,tensilica-xtensa-lx6";
18			reg = <0>;
19			cpu-power-states = <&d3>;
20			i-cache-line-size = <64>;
21			d-cache-line-size = <64>;
22		};
23
24		cpu1: cpu@1 {
25			device_type = "cpu";
26			compatible = "cdns,tensilica-xtensa-lx6";
27			reg = <1>;
28			cpu-power-states = <&d3>;
29		};
30
31		power-states {
32			/* PM_STATE_SOFT_OFF can be entered only by calling
33			 * pm_state_force. The procedure is triggered by IPC
34			 * from the HOST (SET_DX).
35			 */
36			d3: off {
37				compatible = "zephyr,power-state";
38				power-state-name = "soft-off";
39				min-residency-us = <2147483647>;
40				exit-latency-us = <0>;
41			};
42		};
43	};
44
45	sram0: memory@be000000 {
46		device_type = "memory";
47		compatible = "mmio-sram";
48		reg = <0xbe000000 DT_SIZE_K(1920)>;
49	};
50
51	sram1: memory@be800000 {
52		device_type = "memory";
53		compatible = "mmio-sram";
54		reg = <0xbe800000 DT_SIZE_K(64)>;
55	};
56
57	sysclk: system-clock {
58		compatible = "fixed-clock";
59		clock-frequency = <38400000>;
60		#clock-cells = <0>;
61	};
62
63	audioclk: audio-clock {
64		compatible = "fixed-clock";
65		clock-frequency = <24576000>;
66		#clock-cells = <0>;
67	};
68
69	pllclk: pll-clock {
70		compatible = "fixed-clock";
71		clock-frequency = <96000000>;
72		#clock-cells = <0>;
73	};
74
75	clkctl: clkctl {
76		compatible = "intel,adsp-shim-clkctl";
77		adsp-clkctl-clk-wovcro = <0>;
78		adsp-clkctl-clk-lpro = <1>;
79		adsp-clkctl-clk-hpro = <2>;
80		adsp-clkctl-freq-enc = <0x1a 0x20000002 0x80000002>;
81		adsp-clkctl-freq-mask = <0x10 0x20000000 0x80000000>;
82		adsp-clkctl-freq-default = <2>;
83		adsp-clkctl-freq-lowest = <0>;
84		wovcro-supported;
85	};
86
87	IMR1: memory@b0000000 {
88		compatible = "intel,adsp-imr";
89		reg = <0xB0000000 DT_SIZE_M(16)>;
90		block-size = <0x1000>;
91		zephyr,memory-region = "IMR1";
92	};
93
94	soc {
95		lsbpm: lsbpm@71d50 {
96			compatible = "intel,adsp-lsbpm";
97			reg = <0x71d50 0x10>;
98		};
99
100		hsbpm: hsbpm@71d10 {
101			compatible = "intel,adsp-hsbpm";
102			reg = <0x71d10 0x10>;
103		};
104
105		shim: shim@71f00 {
106			compatible = "intel,adsp-shim";
107			reg = <0x71f00 0x100>;
108		};
109
110		mem_window0: mem_window@71a00 {
111			compatible = "intel,adsp-mem-window";
112			reg = <0x71a00 0x8>;
113			offset = <0x4000>;
114			memory = <&sram0>;
115			initialize;
116			read-only;
117		};
118		mem_window1: mem_window@71a08 {
119			compatible = "intel,adsp-mem-window";
120			reg = <0x71a08 0x8>;
121			memory = <&sram0>;
122		};
123
124		mem_window2: mem_window@71a10 {
125			compatible = "intel,adsp-mem-window";
126			reg = <0x71a10 0x8>;
127			memory = <&sram0>;
128		};
129
130		mem_window3: mem_window@71a18 {
131			compatible = "intel,adsp-mem-window";
132			reg = <0x71a18 0x8>;
133			memory = <&sram0>;
134			read-only;
135		};
136
137		timer: timer {
138			compatible = "intel,adsp-timer";
139			syscon = <&shim>;
140		};
141
142		sspbase: ssp_base@71c00 {
143			compatible = "intel,cavs-sspbase";
144			reg = <0x71c00 0x100>;
145		};
146
147		l2lm: l2lm@71d00 {
148			compatible = "intel,cavs-l2lm";
149			reg = <0x71d00 0x20>;
150		};
151
152		adsp_host_ipc: cavs_host_ipc@71e00 {
153			compatible = "intel,adsp-host-ipc";
154			reg = <0x71e00 0x30>;
155			interrupts = <7 0 0>;
156			interrupt-parent = <&cavs_intc0>;
157		};
158
159		core_intc: core_intc@0 {
160			compatible = "cdns,xtensa-core-intc";
161			reg = <0x00 0x400>;
162			interrupt-controller;
163			#interrupt-cells = <3>;
164		};
165
166		cavs_intc0: cavs@78800  {
167			compatible = "intel,cavs-intc";
168			reg = <0x78800 0x10>;
169			interrupt-controller;
170			#interrupt-cells = <3>;
171			interrupts = <6 0 0>;
172			interrupt-parent = <&core_intc>;
173		};
174
175		cavs_intc1: cavs@78810  {
176			compatible = "intel,cavs-intc";
177			reg = <0x78810 0x10>;
178			interrupt-controller;
179			#interrupt-cells = <3>;
180			interrupts = <0xA 0 0>;
181			interrupt-parent = <&core_intc>;
182		};
183
184		cavs_intc2: cavs@78820  {
185			compatible = "intel,cavs-intc";
186			reg = <0x78820 0x10>;
187			interrupt-controller;
188			#interrupt-cells = <3>;
189			interrupts = <0XD 0 0>;
190			interrupt-parent = <&core_intc>;
191		};
192
193		cavs_intc3: cavs@78830  {
194			compatible = "intel,cavs-intc";
195			reg = <0x78830 0x10>;
196			interrupt-controller;
197			#interrupt-cells = <3>;
198			interrupts = <0x10 0 0>;
199			interrupt-parent = <&core_intc>;
200		};
201
202		adsp_idc: idc@1200 {
203			compatible = "intel,adsp-idc";
204			reg = <0x1200 0x80>;
205			interrupts = <8 0 0>;
206			interrupt-parent = <&cavs_intc0>;
207		};
208
209		tlb: tlb@3000 {
210			compatible = "intel,adsp-tlb";
211			reg = <0x3000 0x1000>;
212			paddr-size = <11>;
213		};
214
215		dmic0: dmic0@10000 {
216			compatible = "intel,dai-dmic";
217			reg = <0x10000 0x8000>;
218			shim = <0x71E80>;
219			fifo = <0x0008>;
220			interrupts = <0x08 0 0>;
221			interrupt-parent = <&cavs_intc3>;
222		};
223
224		dmic1: dmic1@10000 {
225			compatible = "intel,dai-dmic";
226			reg = <0x10000 0x8000>;
227			shim = <0x71E80>;
228			fifo = <0x0108>;
229			interrupts = <0x09 0 0>;
230			interrupt-parent = <&cavs_intc3>;
231		};
232
233		/*
234		 * FIXME this is modeling individual alh channels/instances
235		 * with node labels, which has problems. A better representation
236		 * is discussed here:
237		 *
238		 * https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009
239		 */
240		alh0: alh0@71000 {
241			compatible = "intel,alh-dai";
242			reg = <0x00071000 0x00071200>;
243
244			status = "okay";
245		};
246
247		alh1: alh1@71000 {
248			compatible = "intel,alh-dai";
249			reg = <0x00071000 0x00071200>;
250
251			status = "okay";
252		};
253
254		ssp0: ssp@77000 {
255			compatible = "intel,ssp";
256			#address-cells = <1>;
257			#size-cells = <0>;
258			reg = <0x00077000 0x200
259			       0x00078C00 0x008>;
260			interrupts = <0x01 0 0>;
261			interrupt-parent = <&cavs_intc3>;
262			dmas = <&lpgpdma0 2
263				&lpgpdma0 3>;
264			dma-names = "tx", "rx";
265			ssp-index = <0>;
266			status = "okay";
267
268			ssp00: ssp@0 {
269				compatible = "intel,ssp-dai";
270				reg = <0x0>;
271				status = "okay";
272			};
273		};
274
275		ssp1: ssp@77200 {
276			compatible = "intel,ssp";
277			#address-cells = <1>;
278			#size-cells = <0>;
279			reg = <0x00077200 0x200
280			       0x00078C00 0x008>;
281			interrupts = <0x01 0 0>;
282			interrupt-parent = <&cavs_intc3>;
283			dmas = <&lpgpdma0 4
284				&lpgpdma0 5>;
285			dma-names = "tx", "rx";
286			ssp-index = <1>;
287			status = "okay";
288
289			ssp10: ssp@10 {
290				compatible = "intel,ssp-dai";
291				reg = <0x10>;
292				status = "okay";
293			};
294		};
295
296		ssp2: ssp@77400 {
297			compatible = "intel,ssp";
298			#address-cells = <1>;
299			#size-cells = <0>;
300			reg = <0x00077400 0x200
301			       0x00078C00 0x008>;
302			interrupts = <0x02 0 0>;
303			interrupt-parent = <&cavs_intc3>;
304			dmas = <&lpgpdma0 6
305				&lpgpdma0 7>;
306			dma-names = "tx", "rx";
307			ssp-index = <2>;
308			status = "okay";
309
310			ssp20: ssp@20 {
311				compatible = "intel,ssp-dai";
312				reg = <0x20>;
313				status = "okay";
314			};
315		};
316	};
317
318	hdas {
319		#address-cells = <1>;
320		#size-cells = <0>;
321
322		hda0: hda@0 {
323			compatible = "intel,hda-dai";
324			status = "okay";
325			reg = <0>;
326		};
327		hda1: hda@1 {
328			compatible = "intel,hda-dai";
329			status = "okay";
330			reg = <1>;
331		};
332		hda2: hda@2 {
333			compatible = "intel,hda-dai";
334			status = "okay";
335			reg = <2>;
336		};
337		hda3: hda@3 {
338			compatible = "intel,hda-dai";
339			status = "okay";
340			reg = <3>;
341		};
342		hda4: hda@4 {
343			compatible = "intel,hda-dai";
344			status = "okay";
345			reg = <4>;
346		};
347		hda5: hda@5 {
348			compatible = "intel,hda-dai";
349			status = "okay";
350			reg = <5>;
351		};
352		hda6: hda@6 {
353			compatible = "intel,hda-dai";
354			status = "okay";
355			reg = <6>;
356		};
357		hda7: hda@7 {
358			compatible = "intel,hda-dai";
359			status = "okay";
360			reg = <7>;
361		};
362		hda8: hda@8 {
363			compatible = "intel,hda-dai";
364			status = "okay";
365			reg = <8>;
366		};
367		hda9: hda@9 {
368			compatible = "intel,hda-dai";
369			status = "okay";
370			reg = <9>;
371		};
372		hda10: hda@a {
373			compatible = "intel,hda-dai";
374			status = "okay";
375			reg = <0x0a>;
376		};
377		hda11: hda@b {
378			compatible = "intel,hda-dai";
379			status = "okay";
380			reg = <0x0b>;
381		};
382		hda12: hda@c {
383			compatible = "intel,hda-dai";
384			status = "okay";
385			reg = <0x0c>;
386		};
387		hda13: hda@d {
388			compatible = "intel,hda-dai";
389			status = "okay";
390			reg = <0x0d>;
391		};
392		hda14: hda@e {
393			compatible = "intel,hda-dai";
394			status = "okay";
395			reg = <0x0e>;
396		};
397		hda15: hda@f {
398			compatible = "intel,hda-dai";
399			status = "okay";
400			reg = <0x0f>;
401		};
402	};
403};
404