1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ 8 9 #ifndef _ASMLANGUAGE 10 #include <zephyr/sys/util.h> 11 12 /** 13 * DfPMCCH 14 * Power Management / Clock Control (HST) Registers 15 * 16 * These registers block (HST domain) are for general power management 17 * and clock control operation for DSP FW. 18 */ 19 struct ace_dfpmcch { 20 uint32_t dfspsreq; /* Offset: 0x00 */ 21 uint32_t _unused0[3]; 22 uint32_t dfspsrsp; /* Offset: 0x10 */ 23 uint32_t _unused1[1]; 24 uint32_t svcfg; /* Offset: 0x18 */ 25 uint32_t dfltrc; /* Offset: 0x1c */ 26 uint32_t _unused2[8]; 27 }; 28 29 /** 30 * DfPMCCU 31 * Power Management / Clock Control (ULP) Registers 32 * 33 * These registers block (ULP domain) are for general power management 34 * and clock control operation for DSP FW. 35 */ 36 struct ace_dfpmccu { 37 uint32_t dfpmccap; /* Offset: 0x00 */ 38 uint32_t dfhrosccf; /* Offset: 0x04 */ 39 uint32_t dfxosccf; /* Offset: 0x08 */ 40 uint32_t dflrosccf; /* Offset: 0x0c */ 41 uint32_t dfsiorosccf; /* Offset: 0x10 */ 42 uint32_t dfhsiorosccf; /* Offset: 0x14 */ 43 uint32_t dfipllrosccf; /* Offset: 0x18 */ 44 uint32_t dfirosccv; /* Offset: 0x1c */ 45 uint32_t dffbrcfd; /* Offset: 0x20 */ 46 uint32_t dfapllptr; /* Offset: 0x24 */ 47 uint32_t _unused0[20]; 48 uint32_t dfclkctl; /* Offset: 0x78 */ 49 uint32_t dfclksts; /* Offset: 0x7c */ 50 uint32_t dfintclkctl; /* Offset: 0x80 */ 51 uint32_t dfcrosts; /* Offset: 0x84 */ 52 uint32_t dfcrodiv; /* Offset: 0x88 */ 53 uint32_t _unused1[1]; 54 uint16_t dfpwrctl; /* Offset: 0x90 */ 55 uint16_t dfpwrsts; /* Offset: 0x92 */ 56 uint16_t dfpwrctl2; /* Offset: 0x94 */ 57 uint16_t dfpwrsts2; /* Offset: 0x96 */ 58 uint32_t dflpsdmas0; /* Offset: 0x98 */ 59 uint32_t dflpsdmas1; /* Offset: 0x9c */ 60 uint32_t _unused3[1]; 61 uint32_t dfldoctl; /* Offset: 0xa4 */ 62 uint32_t _unused4[2]; 63 uint32_t dflpsalhsso; /* Offset: 0xb0 */ 64 uint32_t dflpsalhss1; /* Offset: 0xb4 */ 65 uint32_t dflpsalhss2; /* Offset: 0xb8 */ 66 uint32_t dflpsalhss3; /* Offset: 0xbc */ 67 uint32_t _unused5[10]; 68 }; 69 70 #define ACE_DfPMCCH (*((volatile struct ace_dfpmcch *)DT_REG_ADDR(DT_NODELABEL(dfpmcch)))) 71 #define ACE_DfPMCCU (*((volatile struct ace_dfpmccu *)DT_REG_ADDR(DT_NODELABEL(dfpmccu)))) 72 73 #define ADSP_TTSCAP_OFFSET 0x00 74 #define ADSP_RTCWC_OFFSET 0x08 75 #define ADSP_DSPWCCTL_OFFSET 0x10 76 #define ADSP_DSPWCSTS_OFFSET 0x12 77 #define ADSP_DSPWCAV_OFFSET 0x18 78 #define ADSP_DSPWC_OFFSET 0x20 79 #define ADSP_DSPWCTCS_OFFSET 0x28 80 #define ADSP_DSPWCT0C_OFFSET 0x30 81 #define ADSP_DSPWCT1C_OFFSET 0x38 82 #define ADSP_TSCTRL_OFFSET 0x40 83 #define ADSP_ISCS_OFFSET 0x44 84 #define ADSP_LSCS_OFFSET 0x48 85 #define ADSP_DWCCS_OFFSET 0x50 86 #define ADSP_ARTCS_OFFSET 0x58 87 #define ADSP_LWCCS_OFFSET 0x60 88 #define ADSP_CLTSYNC_OFFSET 0x70 89 90 #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) 91 92 #define ADSP_SHIM_TSCTRL_NTK BIT(31) 93 #define ADSP_SHIM_TSCTRL_IONTE BIT(30) 94 #define ADSP_SHIM_TSCTRL_DMATS GENMASK(13, 12) 95 #define ADSP_SHIM_TSCTRL_CLNKS GENMASK(11, 10) 96 #define ADSP_SHIM_TSCTRL_HHTSE BIT(7) 97 #define ADSP_SHIM_TSCTRL_LWCS BIT(6) 98 #define ADSP_SHIM_TSCTRL_ODTS BIT(5) 99 #define ADSP_SHIM_TSCTRL_CDMAS GENMASK(4, 0) 100 101 #endif /* _ASMLANGUAGE */ 102 103 #define ACE_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */ 104 105 #define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0) 106 #define ACE_CRODIV_CARCDS(x) ((x) & ACE_CRODIV_CARCDS_MASK) 107 108 #define ACE_CRODIV_CARCDS_MASK GENMASK(7, 0) 109 #define ACE_CRODIV_CARCDS(x) ((x) & ACE_CRODIV_CARCDS_MASK) 110 111 #define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0) 112 #define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0) 113 114 #define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) 115 #define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) 116 117 #define ADSP_DMWBA_ENABLE BIT(0) 118 #define ADSP_DMWBA_READONLY BIT(1) 119 120 #define ADSP_CLKCTL_OSC_SOURCE_MASK (3 << 2) 121 #define ADSP_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28)) 122 123 /** LDO Control */ 124 #define ADSP_DSPRA_ADDRESS (0x71A60) 125 #define ADSP_LPGPDMACxO_ADDRESS(x) (ADSP_DSPRA_ADDRESS + 0x0000 + 0x0002 * (x)) 126 #define ADSP_DSPIOPO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0008) 127 #define ADSP_GENO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x000C) 128 #define ADSP_DSPALHO_ADDRESS (ADSP_DSPRA_ADDRESS + 0x0010) 129 130 #define DSP_INIT_IOPO ADSP_DSPIOPO_ADDRESS 131 #define IOPO_DMIC_FLAG BIT(0) 132 #define IOPO_DSPKOSEL_FLAG BIT(1) 133 #define IOPO_ANCOSEL_FLAG BIT(2) 134 #define IOPO_DMIXOSEL_FLAG BIT(3) 135 #define IOPO_SLIMOSEL_FLAG BIT(4) 136 #define IOPO_SNDWOSEL_FLAG BIT(5) 137 #define IOPO_SLIMDOSEL_FLAG BIT(20) 138 #define IOPO_I2SSEL_MASK (0x7 << 0x8) 139 140 #define DSP_INIT_GENO ADSP_GENO_ADDRESS 141 #define GENO_MDIVOSEL BIT(1) 142 #define GENO_DIOPTOSEL BIT(2) 143 144 #define ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT BIT(1) 145 146 #endif /* ZEPHYR_SOC_INTEL_ADSP_SHIM_H_ */ 147
