Searched full:sre (Results 1 – 9 of 9) sorted by relevance
| /Zephyr-latest/boards/arm/fvp_baser_aemv8r/ |
| D | board.cmake | 15 -C cluster0.gicv3.SRE-enable-action-on-mmap=2
16 -C cluster0.gicv3.SRE-EL2-enable-RAO=1
49 -C cluster0.gicv3.SRE-enable-action-on-mmap=2
50 -C cluster0.gicv3.SRE-EL2-enable-RAO=1
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,mcux-rt11xx-pinctrl.yaml | 30 slew-rate: SRE=<enum_idx>
39 SRE=0
88 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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| D | nxp,imx7d-pinctrl.yaml | 17 slew-rate: SRE=<enum idx>
26 SRE=<slew-rate>,
76 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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| D | nxp,imx8m-pinctrl.yaml | 29 slew-rate: SRE=<enum_idx>
39 SRE=<slew-rate>,
104 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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| D | nxp,mcux-rt-pinctrl.yaml | 32 slew-rate: SRE=<enum_idx>
44 SRE=<slew-rate>,
136 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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| D | nxp,imx8mp-pinctrl.yaml | 40 SRE=<slew-rate>,
92 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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| D | openisa,rv32m1-pinctrl.yaml | 62 Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
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| D | nxp,port-pinctrl.yaml | 73 Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
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| D | nxp,imx93-pinctrl.yaml | 100 Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
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