1# Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
2# Copyright (c) 2022, NXP
3# SPDX-License-Identifier: Apache-2.0
4
5description: |
6  OpenISA RV32M1 pinctrl node. This node will define pin configurations in pin groups,
7  and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
8  within the pin configuration defines the pin configuration for a peripheral,
9  and each numbered subgroup in the pin group defines all the pins for that
10  peripheral with the same configuration properties. The 'pins' property in
11  a group selects the pins to be configured, and the remaining properties set
12  configuration values for those pins. Here is an example group for UART0 pins:
13
14  uart0_default: uart0_default {
15    group0 {
16      pinmux = <RV32M1_MUX('C', 7, 3)>,
17               <RV32M1_MUX('C', 8, 3)>;
18      drive-strength = "low";
19      slew-rate = "fast";
20    };
21  };
22
23  If only the required properties are supplied, the pin configuration register
24  will be assigned the following values:
25  PCR_PS=0,
26  PCR_PE=0,
27  PCR_ODE=0,
28  PCR_SRE=<slew-rate selection>,
29  PCR_PFE=0
30
31compatible: "openisa,rv32m1-pinctrl"
32
33include: base.yaml
34
35child-binding:
36  description: RV32M1 pin controller pin group
37  child-binding:
38    description: |
39      RV31M1 pin controller pin configuration node
40
41    include:
42      - name: pincfg-node.yaml
43        property-allowlist:
44          - drive-open-drain
45          - bias-pull-up
46          - bias-pull-down
47
48    properties:
49      pinmux:
50        required: true
51        type: array
52        description: |
53          Pin mux selections for this group. See the SoC level pinctrl DTSI file
54          in the OpenISA HAL for a defined list of these options
55      slew-rate:
56        required: true
57        type: string
58        enum:
59          - "fast"
60          - "slow"
61        description: |
62          Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
63          0 SRE_0_fast- fast slew rate when pin is configured as output
64          1 SRE_1_slow- slow slew rate when pin is configured as output
65      openisa,passive-filter:
66        type: boolean
67        description: |
68          Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.
69