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/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml5 description: Microchip XEC QMSPI controller with local DMA
7 compatible: "microchip,xec-qmspi-ldma"
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
51 Use QMSPI CS0# or CS1#. Port 0 supports both chip selects.
57 Delay in QMSPI main clocks from CS# assertion to first clock edge.
59 for QMSPI input clock frequency.
64 Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
66 for QMSPI input clock frequency.
71 Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
73 documentation for QMSPI input clock frequency.
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Dmicrochip,xec-qmspi.yaml4 description: Microchip XEC QMSPI controller
6 compatible: "microchip,xec-qmspi"
38 description: QMSPI lines 1, 2, or 4
43 description: Use QMSPI CS0# or CS1#
/Zephyr-latest/drivers/spi/
DKconfig.xec_qmspi1 # Microchip XEC QMSPI
7 bool "Microchip MEC15xx XEC QMSPI driver"
12 Enable support for Microchip MEC15xx XEC QMSPI driver.
15 bool "Microchip XEC MEC17xx QMSPI LDMA driver"
19 Enable support for Microchip MEC17xx QMSPI with local DMA driver.
Dspi_xec_qmspi_ldma.c33 /* MEC172x QMSPI controller SPI Mode 3 signalling has an anomaly where
132 * reset QMSPI controller with save/restore of timing registers.
133 * Some QMSPI timing register may be modified by the Boot-ROM OTP
177 /* Program QMSPI frequency divider field in the mode register.
178 * MEC172x QMSPI input clock source is the Fast Peripheral domain whose
181 * rate of fast peripheral domain. MEC172x QMSPI clock divider has
228 * QMSPI has three controls, CPOL, CPHA for output and CPHA for input.
232 * Data sheet recommends when QMSPI set at max. SPI frequency (48MHz).
272 * QMSPI HW support single, dual, and quad.
273 * Return QMSPI Control/Descriptor register encoded value.
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Dspi_xec_qmspi.c67 * Program QMSPI frequency.
68 * MEC1501 base frequency is 48MHz. QMSPI frequency divider field in the
109 * Data sheet recommends when QMSPI set at max. SPI frequency (48MHz).
140 * QMSPI HW support single, dual, and quad.
141 * Return QMSPI Control/Descriptor register encoded value.
173 * Configure QMSPI.
174 * NOTE: QMSPI can control two chip selects. At this time we use CS0# only.
242 * Transmit dummy clocks - QMSPI will generate requested number of
247 * QMSPI unit size set to bits.
301 * Return QMSPI unit size of the number of units field in QMSPI
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/Zephyr-latest/soc/microchip/mec/mec15xx/
Dsoc_espi_saf_v1.h40 * Default QMSPI clock divider and chip select timing.
41 * QMSPI master clock is 48MHz AHB clock.
46 /* SAF QMSPI programming */
60 /* QMSPI descriptors 12-15 for all SPI flash devices */
64 * QMSPI descriptors 12-13 are exit continuous mode
84 * QMSPI descriptors 14-15 are poll 16-bit flash status
137 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
138 * e = First QMSPI descriptor index for enter continuous mode chain
139 * r = First QMSPI descriptor index for continuous mode read chain
140 * s = Index of QMSPI descriptor in continuous mode read chain that
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/Zephyr-latest/soc/microchip/mec/mec172x/
Dsoc_espi_saf_v2.h39 * Default QMSPI clock divider and chip select timing.
40 * QMSPI master clock is either 96 or 48 MHz depending upon
45 /* SAF V2 implements dynamically changing the QMSPI clock
56 /* SAF QMSPI programming */
70 /* QMSPI descriptors 12-15 for all SPI flash devices */
72 /* QMSPI descriptors 12-13 are exit continuous mode */
108 * QMSPI descriptors 14-15 are poll 16-bit flash status
161 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value
162 * e = First QMSPI descriptor index for enter continuous mode chain
163 * r = First QMSPI descriptor index for continuous mode read chain
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/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec_v2.c41 /* Get QMSPI 0 encoded GIRQ information */
57 * QMSPI controller register block base address
209 * Take over and re-initialize QMSPI for use by SAF HW engine.
210 * When SAF is activated, QMSPI registers are controlled by SAF
211 * HW engine. CPU no longer has access to QMSPI registers.
212 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
214 * 2. Put QMSPI controller in a known state by performing a soft reset.
215 * 3. Clear QMSPI GIRQ status
216 * 4. Configure QMSPI interface control for SAF.
218 * 6. Enable transfer done interrupt in QMSPI
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Despi_saf_mchp_xec.c40 * QMSPI controller register block base address
192 * Take over and re-initialize QMSPI for use by SAF HW engine.
193 * When SAF is activated, QMSPI registers are controlled by SAF
194 * HW engine. CPU no longer has access to QMSPI registers.
195 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
197 * 2. Put QMSPI controller in a known state by performing a soft reset.
198 * 3. Clear QMSPI GIRQ status
199 * 4. Configure QMSPI interface control for SAF.
201 * 6. Enable transfer done interrupt in QMSPI
202 * 7. Enable QMSPI SAF mode
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/Zephyr-latest/samples/boards/microchip/mec172xevb_assy6906/qmspi_ldma/
Dsample.yaml2 description: mec172xevb_assy6906 QMSPI-LDMA testing
Dmec172xevb_assy6906.overlay65 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dmec172xevb_assy6906.overlay9 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/samples/drivers/spi_flash/boards/
Dmec172xevb_assy6906.overlay9 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_qspi.h37 /* QMSPI transmit and receive FIFO lengths */
41 /* QMSPI Local DMA channels */
401 /** @brief QMSPI Local DMA channel registers */
409 /** @brief QMSPI controller. Size = 368(0x170) */
/Zephyr-latest/dts/bindings/pinctrl/
Dmicrochip,mec5-pinctrl.yaml44 We want to use the shared SPI port of the MEC172x QMSPI controller
Dmicrochip,xec-pinctrl.yaml45 We want to use the shared SPI port of the MEC172x QMSPI controller
/Zephyr-latest/soc/microchip/mec/
DKconfig199 This three bit value corresponds to the QMSPI controllers clock idle and
/Zephyr-latest/boards/microchip/mec172xmodular_assy6930/
Dmec172xmodular_assy6930.dts180 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/
Dmec172xevb_assy6906.dts202 compatible = "microchip,xec-qmspi-ldma";
/Zephyr-latest/samples/drivers/espi/src/
Dmain.c127 * Use QMSPI frequency, chip select timing, and signal sampling configured
128 * by QMSPI driver.
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi467 compatible = "microchip,xec-qmspi";
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c913 * ARM Core, QMSPI, and PK use turbo clock. All other peripherals
/Zephyr-latest/dts/arm/microchip/mec152x/
Dmec152xhsz-pinctrl.dtsi532 /* MEC152x QMSPI Port 2 can be external pins named gpspi_xxx or
/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst1114 * :dtcompatible:`microchip,xec-qmspi`
1176 * :dtcompatible:`microchip,xec-qmspi`
Drelease-notes-3.3.rst1337 - :dtcompatible:`microchip,xec-qmspi-full-duplex`
1642 - :dtcompatible:`microchip,xec-qmspi-ldma`: