Searched full:plln (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32f7-pll-clock.yaml | 15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f2-pll-clock.yaml | 15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32g4-pll-clock.yaml | 18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32f4-pll-clock.yaml | 17 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32g0-pll-clock.yaml | 18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32u0-pll-clock.yaml | 18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32wba-pll-clock.yaml | 20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32wb-pll-clock.yaml | 21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32l4-pll-clock.yaml | 21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| D | st,stm32u5-pll-clock.yaml | 20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_h7.c | 1014 * PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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