| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 193 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
194 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
195 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay)
197 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
198 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
199 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p)
200 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1)
201 #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q)
202 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1)
203 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r)
[all …]
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32h7rs-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
20 f(PLL_Tx) = f(VCOx clock) / PLLTx -> pllx_t_ck (only for PLL2)
39 PLL division factor for pllx_t_ck : valid for PLL2
|
| D | st,stm32f105-pll-clock.yaml | 7 Takes one of clk_hse, pll2 or clk_hsi as input clock.
9 pll2, configurable prescaler is used.
17 f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse or pll2
|
| D | st,stm32f105-pll2-clock.yaml | 5 PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
14 compatible: "st,stm32f105-pll2-clock"
|
| D | st,stm32u5-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
72 No restrictions for PLL2 and PLL3
|
| D | st,stm32f100-pll-clock.yaml | 9 pll2, configurable prescaler is used.
|
| D | st,stm32h7-pll-clock.yaml | 7 It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 65 /* AUDIO PLL2 configuration */
71 .postDiv = 1U, /* AUDIO PLL2 frequency = 722534399HZ */
84 * the SYSTEM PLL2 in SOC_ClockInit()
90 /* Init AUDIO PLL2 to run at 722534399HZ */ in SOC_ClockInit()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/ |
| D | spi1_pll2p_1.overlay | 12 &pll2 {
|
| D | core_init.overlay | 50 &pll2 {
|
| /Zephyr-latest/dts/arm/st/f1/ |
| D | stm32f105.dtsi | 20 pll2: pll2 { label
22 compatible = "st,stm32f105-pll2-clock";
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 67 /* SYSTEM PLL2 configuration */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
96 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */ in SOC_ClockInit()
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32f1.c | 124 * @brief Set up pll2 configuration
155 /* Check PLL2 source */ in config_pll2()
|
| D | clock_stm32_ll_common.c | 582 * Disable PLL2 after switching to HSI for SysClk in set_up_plls()
584 * since PLL source can be PLL2. in set_up_plls()
588 /* Wait for PLL2 to be disabled */ in set_up_plls()
593 /* Enable PLL2 */ in set_up_plls()
596 /* Wait for PLL2 ready */ in set_up_plls()
|
| D | clock_stm32_ll_h5.c | 506 /* Configure PLL2 source */ in set_up_plls()
526 /* Set VCO Input before enabling the PLL, depends on the freq of the PLL2 */ in set_up_plls()
528 /* Select VCO freq range before enabling the PLL, depends on the freq of the PLL2 */ in set_up_plls()
554 /* Init PLL2 source to None */ in set_up_plls()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | clear_clocks.overlay | 49 &pll2 {
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | clear_clocks.overlay | 45 &pll2 {
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt118x/ |
| D | soc.c | 152 /* Init Sys Pll2. */ in clock_init()
154 /* Init System Pll2 pfd0. */ in clock_init()
156 /* Init System Pll2 pfd1. */ in clock_init()
158 /* Init System Pll2 pfd2. */ in clock_init()
160 /* Init System Pll2 pfd3. */ in clock_init()
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt11xx/ |
| D | soc.c | 276 /* Init Sys Pll2. */ in clock_init()
279 /* Init System Pll2 pfd0. */ in clock_init()
282 /* Init System Pll2 pfd1. */ in clock_init()
285 /* Init System Pll2 pfd2. */ in clock_init()
288 /* Init System Pll2 pfd3. */ in clock_init()
509 * PLL2 is fixed at 528MHz. Use desired panel clock clock to in clock_init()
|
| /Zephyr-latest/dts/arm/renesas/ra/ra6/ |
| D | r7fa6e10x.dtsi | 169 pll2: pll2 { label
173 /* PLL2 */
|
| D | r7fa6m4ax.dtsi | 278 pll2: pll2 { label
282 /* PLL2 */
|
| /Zephyr-latest/dts/arm/renesas/ra/ra8/ |
| D | r7fa8m1xh.dtsi | 82 pll2: pll2 { label
86 /* PLL2 */
|
| D | r7fa8d1xh.dtsi | 112 pll2: pll2 { label
116 /* PLL2 */
|
| /Zephyr-latest/dts/arm/renesas/ra/ra4/ |
| D | r7fa4m3ax.dtsi | 204 pll2: pll2 { label
|
| D | r7fa4m2ax.dtsi | 191 pll2: pll2 { label
|
