Home
last modified time | relevance | path

Searched full:interrupt (Results 1 – 25 of 2360) sorted by relevance

12345678910>>...95

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp32s3-xtensa-intmux.h10 #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/
11 #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI */
13 #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/
16 #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/
17 #define RWBT_INTR_SOURCE 7 /* interrupt of RWBT, level*/
18 #define RWBLE_INTR_SOURCE 8 /* interrupt of RWBLE, level*/
19 #define RWBT_NMI_SOURCE 9 /* interrupt of RWBT, NMI*/
20 #define RWBLE_NMI_SOURCE 10 /* interrupt of RWBLE, NMI*/
21 #define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/
[all …]
Desp-esp32c6-intmux.h10 #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/
11 #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI*/
13 #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/
15 #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/
16 #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/
21 #define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/
24 #define EFUSE_INTR_SOURCE 14 /* interrupt of efuse, level, not likely to use*/
36 #define ASSIST_DEBUG_INTR_SOURCE 26 /* interrupt of Assist debug module, LEVEL*/
40 #define GPIO_INTR_SOURCE 30 /* interrupt of GPIO, level*/
41 #define GPIO_NMI_SOURCE 31 /* interrupt of GPIO, NMI*/
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6_cm0.dtsi29 intmux_ch0: interrupt-controller@0 {
32 #interrupt-cells = <2>;
33 interrupt-controller;
37 intmux_ch1: interrupt-controller@1 {
40 #interrupt-cells = <2>;
41 interrupt-controller;
45 intmux_ch2: interrupt-controller@2 {
48 #interrupt-cells = <2>;
49 interrupt-controller;
53 intmux_ch3: interrupt-controller@3 {
[all …]
/Zephyr-latest/tests/kernel/interrupt/
Dmultilevel_irq.overlay11 test_cpu_intc: interrupt-controller {
14 #interrupt-cells = < 0x01 >;
15 interrupt-controller;
18 test_l1_irq: interrupt-controller@bbbbcccc {
21 interrupt-controller;
22 #interrupt-cells = <2>;
24 interrupt-parent = <&test_cpu_intc>;
27 test_l2_irq: interrupt-controller@bbbccccc {
30 interrupt-controller;
31 #interrupt-cells = <2>;
[all …]
Dtestcase.yaml2 arch.interrupt:
8 - interrupt
10 arch.interrupt.qemu_cortex_m0:
14 - interrupt
18 arch.interrupt.minimallibc:
25 - interrupt
29 arch.interrupt.qemu_cortex_m0.minimallibc:
34 - interrupt
49 # test needs 2 working interrupt lines
55 - interrupt
[all …]
/Zephyr-latest/soc/arm/musca/b1/
Dsystem_cmsdk_musca_b1.h19 /* ================ Interrupt Number Definition …
23 /* =========================================== Core Specific Interrupt Numbers ==================…
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
30 …SVCall_IRQn = -5, /* -5 SV Call Interrupt …
31 …DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt …
[all …]
/Zephyr-latest/soc/arm/musca/s1/
Dsystem_cmsdk_musca_s1.h19 /* ================ Interrupt Number Definition …
23 /* =========================================== Core Specific Interrupt Numbers ==================…
24 …NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt …
25 …HardFault_IRQn = -13, /* -13 HardFault Interrupt …
26 …MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt …
27 …BusFault_IRQn = -11, /* -11 Bus Fault Interrupt …
28 …UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt …
29 …SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt …
30 …SVCall_IRQn = -5, /* -5 SV Call Interrupt …
31 …DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt …
[all …]
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8qxp.dtsi10 irqsteer: interrupt-controller@51080000 {
18 master0: interrupt-controller@0 {
21 interrupt-controller;
22 #interrupt-cells = <1>;
26 master1: interrupt-controller@1 {
29 interrupt-controller;
30 #interrupt-cells = <1>;
34 master2: interrupt-controller@2 {
37 interrupt-controller;
38 #interrupt-cells = <1>;
[all …]
Dnxp_imx8qm.dtsi11 irqsteer: interrupt-controller@510a0000 {
19 master0: interrupt-controller@0 {
22 interrupt-controller;
23 #interrupt-cells = <1>;
27 master1: interrupt-controller@1 {
30 interrupt-controller;
31 #interrupt-cells = <1>;
35 master2: interrupt-controller@2 {
38 interrupt-controller;
39 #interrupt-cells = <1>;
[all …]
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Driscv_plic.h9 * @brief Driver for Platform Level Interrupt Controller (PLIC)
18 * @brief Enable interrupt
20 * @param irq Multi-level encoded interrupt ID
25 * @brief Disable interrupt
27 * @param irq Multi-level encoded interrupt ID
32 * @brief Check if an interrupt is enabled
34 * @param irq Multi-level encoded interrupt ID
35 * @return Returns true if interrupt is enabled, false otherwise
40 * @brief Set interrupt priority
42 * @param irq Multi-level encoded interrupt ID
[all …]
Dintc_esp32.h17 * Interrupt allocation flags - These flags can be used to specify
18 * which interrupt qualities the code calling esp_intr_alloc* needs.
30 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
31 #define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */
33 #define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */
48 * Get the interrupt flags from the supplied priority.
54 * Check interrupt flags from input and filter unallowed values.
60 * are routed through the interrupt mux. Apart from these sources, each core also has some internal
61 * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
64 #define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Xtensa timer 0 interrupt source */
[all …]
Driscv_clic.h9 * @brief Driver for Core-Local Interrupt Controller (CLIC)
16 * @brief Enable interrupt
18 * @param irq interrupt ID
23 * @brief Disable interrupt
25 * @param irq interrupt ID
30 * @brief Check if an interrupt is enabled
32 * @param irq interrupt ID
33 * @return Returns true if interrupt is enabled, false otherwise
38 * @brief Set interrupt priority
40 * @param irq interrupt ID
[all …]
Dnxp_pint.h8 * @brief Driver for Pin interrupt and pattern match engine in NXP MCUs
10 * The Pin interrupt and pattern match engine (PINT) supports
15 * This driver currently only supports the pin interrupt feature of
25 * @brief Pin interrupt sources
27 * Pin interrupt sources available for use.
30 /* Do not generate Pin Interrupt */
32 /* Generate Pin Interrupt on rising edge */
34 /* Generate Pin Interrupt on falling edge */
36 /* Generate Pin Interrupt on both edges */
38 /* Generate Pin Interrupt on low level */
[all …]
Dgic.h9 * @brief Driver for ARM Generic Interrupt Controller
11 * The Generic Interrupt Controller (GIC) is the default interrupt controller
38 * 0x004 Interrupt Controller Type Register
52 * 0x080 Interrupt Group Registers
59 * 0x100 Interrupt Set-Enable Registers
66 * 0x180 Interrupt Clear-Enable Registers
73 * 0x200 Interrupt Set-Pending Registers
80 * 0x280 Interrupt Clear-Pending Registers
87 * 0x300 Interrupt Set-Active Registers
95 * 0x380 Interrupt Clear-Active Registers
[all …]
Dintc_esp32c3.h14 * Interrupt allocation flags - These flags can be used to specify
15 * which interrupt qualities the code calling esp_intr_alloc* needs.
26 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */
27 #define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */
29 #define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */
44 * Get the interrupt flags from the supplied priority.
50 * Check interrupt flags from input and filter unallowed values.
55 /* Function prototype for interrupt handler function */
59 * @brief Initializes interrupt table to its defaults
64 * @brief Allocate an interrupt with the given parameters.
[all …]
Dintc_eirq_nxp_s32.h8 * @brief Driver for External interrupt/event controller in NXP S32 MCUs
22 /** Interrupt triggered on rising edge */
24 /** Interrupt triggered on falling edge */
26 /** Interrupt triggered on either edge */
31 * @brief Unset interrupt callback
34 * @param irq interrupt number
39 * @brief Set callback for an interrupt associated with a given pin
42 * @param irq interrupt number
43 * @param pin GPIO pin associated with the interrupt
48 * @retval -EBUSY if callback for the interrupt is already set
[all …]
/Zephyr-latest/dts/riscv/openisa/
Drv32m1_ri5cy.dtsi57 interrupt-parent = <&event0>;
62 interrupt-parent = <&event0>;
67 interrupt-parent = <&event0>;
71 interrupt-parent = <&event0>;
75 interrupt-parent = <&event0>;
79 interrupt-parent = <&event0>;
83 interrupt-parent = <&event0>;
87 interrupt-parent = <&event0>;
93 interrupt-parent = <&intmux0_ch0>;
98 interrupt-parent = <&intmux0_ch1>;
[all …]
Drv32m1_zero_riscy.dtsi59 interrupt-parent = <&event1>;
64 interrupt-parent = <&event1>;
68 interrupt-parent = <&event1>;
72 interrupt-parent = <&event1>;
76 interrupt-parent = <&event1>;
80 interrupt-parent = <&event1>;
84 interrupt-parent = <&event1>;
88 interrupt-parent = <&event1>;
92 interrupt-parent = <&intmux1_ch0>;
97 interrupt-parent = <&intmux1_ch0>;
[all …]
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.dw5 bool "Designware Interrupt Controller for ACE"
10 Designware Interrupt Controller used by ACE.
13 bool "Designware Interrupt Controller"
18 Designware Interrupt Controller can be used as a 2nd level interrupt
19 controller which combines several sources of interrupt into one line
20 that is then routed to the 1st level interrupt controller.
26 string "Name for Designware Interrupt Controller"
29 Give a name for the instance of Designware Interrupt Controller
36 the ISRs for Designware Interrupt Controller are assigned.
39 int "Init priority for DW interrupt controller"
[all …]
DKconfig.multilevel1 # Multilevel interrupt configuration
8 bool "Multi-level interrupt support"
13 levels are used, a second level interrupt aggregator would combine
15 interrupt controller. If three levels are used, a third level
17 second level. The number of interrupt levels is usually determined
18 by the hardware. (The term "aggregator" here means "interrupt
23 int "Total number of first level interrupt bits"
27 The number of bits to use of the 32 bit interrupt mask for first
31 int "Max IRQs per interrupt aggregator"
35 The maximum number of interrupt inputs to any aggregator in the
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10 SIUL2 EIRQ interrupt controller.
12 To route external interrupts to the WKPU interrupt controller, the GPIO
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
23 Explicitly specifying the routing of a GPIO interrupt to a particular
24 interrupt controller allows for the allocation of distinct interrupt
26 the fact that each interrupt controller features its own interrupt vector.
28 the interrupt controller configured with a lower priority compared to the one
29 designated for the data-ready interrupt originating from a sensor. This
[all …]
/Zephyr-latest/soc/arm/beetle/
DCMSDK_BEETLE.h20 /* ------------------------- Interrupt Number Definition ------------------------ */
25 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
26 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
27 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
28 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
29 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
30 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
31 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
32 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
33 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dcypress,psoc6-intmux.yaml6 Cypress Interrupt Multiplex
14 4 interrupt sources by grouping intmux channels. These means that each byte
16 interrupt source in the multiplexer. The multiplexer is placed before
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
20 On a general view, the below represents the Interrupt Multiplexer
23 The vector number selects the PSOC 6 peripheral interrupt source for the
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
32 sources and the proper NVIC interrupt order. With that, the system configures
33 the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
38 The below fragment configure the GPIO Port 0 to generate an interrupt at
[all …]
/Zephyr-latest/tests/drivers/counter/counter_basic_api/sysbuild/vpr_launcher/boards/
Dnrf54h20dk_nrf54h20_cpuapp.overlay5 interrupt-parent = <&cpuppr_clic>;
10 interrupt-parent = <&cpuppr_clic>;
15 interrupt-parent = <&cpuppr_clic>;
20 interrupt-parent = <&cpuppr_clic>;
25 interrupt-parent = <&cpuppr_clic>;
30 interrupt-parent = <&cpuppr_clic>;
35 interrupt-parent = <&cpuppr_clic>;
40 interrupt-parent = <&cpuppr_clic>;
45 interrupt-parent = <&cpuppr_clic>;
50 interrupt-parent = <&cpuppr_clic>;
/Zephyr-latest/dts/riscv/qemu/
Dvirt-riscv.dtsi29 interrupt-parent = < &plic >;
46 hlic0: interrupt-controller {
49 #interrupt-cells = < 0x01 >;
50 interrupt-controller;
60 hlic1: interrupt-controller {
63 #interrupt-cells = < 0x01 >;
64 interrupt-controller;
74 hlic2: interrupt-controller {
77 #interrupt-cells = < 0x01 >;
78 interrupt-controller;
[all …]

12345678910>>...95