1/*
2 * Copyright (c) 2020 Cobham Gaisler AB
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/*
8 * This file is based on:
9 *   qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
10 *   dtc virt.dtb > virt.dtsi
11 */
12
13/dts-v1/;
14
15/ {
16	#address-cells = < 0x01 >;
17	#size-cells = < 0x01 >;
18	compatible = "riscv-virtio";
19	model = "riscv-virtio,qemu";
20
21	flash@20000000 {
22		bank-width = < 0x04 >;
23		reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
24		compatible = "cfi-flash";
25	};
26
27	uart0: uart@10000000 {
28		interrupts = < 0x0a 1 >;
29		interrupt-parent = < &plic >;
30		clock-frequency = < 0x384000 >;
31		reg = < 0x10000000 0x100 >;
32		compatible = "ns16550";
33		reg-shift = < 0 >;
34	};
35
36	cpus {
37		#address-cells = < 0x01 >;
38		#size-cells = < 0x00 >;
39
40		cpu@0 {
41			device_type = "cpu";
42			reg = < 0x00 >;
43			status = "okay";
44			compatible = "qemu,riscv-virt", "riscv";
45
46			hlic0: interrupt-controller {
47				compatible = "riscv,cpu-intc";
48				#address-cells = <0>;
49				#interrupt-cells = < 0x01 >;
50				interrupt-controller;
51			};
52		};
53
54		cpu@1 {
55			device_type = "cpu";
56			reg = < 0x01 >;
57			status = "okay";
58			compatible = "qemu,riscv-virt", "riscv";
59
60			hlic1: interrupt-controller {
61				compatible = "riscv,cpu-intc";
62				#address-cells = <0>;
63				#interrupt-cells = < 0x01 >;
64				interrupt-controller;
65			};
66		};
67
68		cpu@2 {
69			device_type = "cpu";
70			reg = < 0x02 >;
71			status = "okay";
72			compatible = "qemu,riscv-virt", "riscv";
73
74			hlic2: interrupt-controller {
75				compatible = "riscv,cpu-intc";
76				#address-cells = <0>;
77				#interrupt-cells = < 0x01 >;
78				interrupt-controller;
79			};
80		};
81
82		cpu@3 {
83			device_type = "cpu";
84			reg = < 0x03 >;
85			status = "okay";
86			compatible = "qemu,riscv-virt", "riscv";
87
88			hlic3: interrupt-controller {
89				compatible = "riscv,cpu-intc";
90				#address-cells = <0>;
91				#interrupt-cells = < 0x01 >;
92				interrupt-controller;
93			};
94		};
95
96		cpu@4 {
97			device_type = "cpu";
98			reg = < 0x04 >;
99			status = "okay";
100			compatible = "qemu,riscv-virt", "riscv";
101
102			hlic4: interrupt-controller {
103				compatible = "riscv,cpu-intc";
104				#address-cells = <0>;
105				#interrupt-cells = < 0x01 >;
106				interrupt-controller;
107			};
108		};
109
110		cpu@5 {
111			device_type = "cpu";
112			reg = < 0x05 >;
113			status = "okay";
114			compatible = "qemu,riscv-virt", "riscv";
115
116			hlic5: interrupt-controller {
117				compatible = "riscv,cpu-intc";
118				#address-cells = <0>;
119				#interrupt-cells = < 0x01 >;
120				interrupt-controller;
121			};
122		};
123
124		cpu@6 {
125			device_type = "cpu";
126			reg = < 0x06 >;
127			status = "okay";
128			compatible = "qemu,riscv-virt", "riscv";
129
130			hlic6: interrupt-controller {
131				compatible = "riscv,cpu-intc";
132				#address-cells = <0>;
133				#interrupt-cells = < 0x01 >;
134				interrupt-controller;
135			};
136		};
137
138		cpu@7 {
139			device_type = "cpu";
140			reg = < 0x07 >;
141			status = "okay";
142			compatible = "qemu,riscv-virt", "riscv";
143
144			hlic7: interrupt-controller {
145				compatible = "riscv,cpu-intc";
146				#address-cells = <0>;
147				#interrupt-cells = < 0x01 >;
148				interrupt-controller;
149			};
150		};
151	};
152
153	ram0: memory@80000000 {
154		device_type = "memory";
155		reg = < 0x80000000 0x10000000 >;
156	};
157
158	soc {
159		#address-cells = < 0x01 >;
160		#size-cells = < 0x01 >;
161		compatible = "simple-bus";
162		ranges;
163
164		plic: interrupt-controller@c000000 {
165			riscv,max-priority = <7>;
166			riscv,ndev = < 1024 >;
167			reg = <0x0c000000 0x04000000>;
168			interrupts-extended = <
169				&hlic0 0x0b &hlic0 0x09
170				&hlic1 0x0b &hlic1 0x09
171				&hlic2 0x0b &hlic2 0x09
172				&hlic3 0x0b &hlic3 0x09
173				&hlic4 0x0b &hlic4 0x09
174				&hlic5 0x0b &hlic5 0x09
175				&hlic6 0x0b &hlic6 0x09
176				&hlic7 0x0b &hlic7 0x09
177			>;
178			interrupt-controller;
179			compatible = "sifive,plic-1.0.0";
180			#address-cells = < 0x00 >;
181			#interrupt-cells = < 0x02 >;
182		};
183
184		clint: clint@2000000 {
185			compatible = "sifive,clint0";
186			reg = <0x2000000 0x10000>;
187			interrupts-extended = <&hlic0 0x03 &hlic0 0x07
188					       &hlic1 0x03 &hlic1 0x07
189					       &hlic2 0x03 &hlic2 0x07
190					       &hlic3 0x03 &hlic3 0x07
191					       &hlic4 0x03 &hlic4 0x07
192					       &hlic5 0x03 &hlic5 0x07
193					       &hlic6 0x03 &hlic6 0x07
194					       &hlic7 0x03 &hlic7 0x07>;
195		};
196	};
197};
198