1 /* 2 * Copyright (c) 2009-2016 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * This file is derivative of CMSIS V5.00 ARMCM3.h 9 */ 10 11 12 #ifndef CMSDK_BEETLE_H 13 #define CMSDK_BEETLE_H 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 20 /* ------------------------- Interrupt Number Definition ------------------------ */ 21 22 typedef enum IRQn 23 { 24 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ 25 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 26 HardFault_IRQn = -13, /* 3 HardFault Interrupt */ 27 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ 28 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ 29 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ 30 SVCall_IRQn = -5, /* 11 SV Call Interrupt */ 31 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ 32 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ 33 SysTick_IRQn = -1, /* 15 System Tick Interrupt */ 34 35 /* --------------------- CMSDK_BEETLE Specific Interrupt Numbers ---------------- */ 36 UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ 37 Spare_IRQn = 1, /* Undefined */ 38 UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ 39 I2C0_IRQn = 3, /* I2C 0 Interrupt */ 40 I2C1_IRQn = 4, /* I2C 1 Interrupt */ 41 RTC_IRQn = 5, /* RTC Interrupt */ 42 PORT0_ALL_IRQn = 6, /* GPIO Port 0 combined Interrupt */ 43 PORT1_ALL_IRQn = 7, /* GPIO Port 1 combined Interrupt */ 44 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */ 45 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */ 46 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */ 47 SPI0_IRQn = 11, /* SPI 0 Interrupt */ 48 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */ 49 SPI1_IRQn = 13, /* SPI 1 Interrupt */ 50 QSPI_IRQn = 14, /* QUAD SPI Interrupt */ 51 DMA_IRQn = 15, /* Reserved for DMA Interrupt */ 52 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */ 53 PORT0_1_IRQn = 17, /* There are 16 pins in total */ 54 PORT0_2_IRQn = 18, 55 PORT0_3_IRQn = 19, 56 PORT0_4_IRQn = 20, 57 PORT0_5_IRQn = 21, 58 PORT0_6_IRQn = 22, 59 PORT0_7_IRQn = 23, 60 PORT0_8_IRQn = 24, 61 PORT0_9_IRQn = 25, 62 PORT0_10_IRQn = 26, 63 PORT0_11_IRQn = 27, 64 PORT0_12_IRQn = 28, 65 PORT0_13_IRQn = 29, 66 PORT0_14_IRQn = 30, 67 PORT0_15_IRQn = 31, 68 SYSERROR_IRQn = 32, /* System Error Interrupt */ 69 EFLASH_IRQn = 33, /* Embedded Flash Interrupt */ 70 LLCC_TXCMD_EMPTY_IRQn = 34, /* t.b.a */ 71 LLCC_TXEVT_EMPTY_IRQn = 35, /* t.b.a */ 72 LLCC_TXDMAH_DONE_IRQn = 36, /* t.b.a */ 73 LLCC_TXDMAL_DONE_IRQn = 37, /* t.b.a */ 74 LLCC_RXCMD_VALID_IRQn = 38, /* t.b.a */ 75 LLCC_RXEVT_VALID_IRQn = 39, /* t.b.a */ 76 LLCC_RXDMAH_DONE_IRQn = 40, /* t.b.a */ 77 LLCC_RXDMAL_DONE_IRQn = 41, /* t.b.a */ 78 PORT2_ALL_IRQn = 42, /* GPIO Port 2 combined Interrupt */ 79 PORT3_ALL_IRQn = 43, /* GPIO Port 3 combined Interrupt */ 80 TRNG_IRQn = 44, /* Random number generator Interrupt */ 81 } IRQn_Type; 82 83 84 /* ================================================================================ */ 85 /* ================ Processor and Core Peripheral Section ================ */ 86 /* ================================================================================ */ 87 88 /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ 89 #define __CM3_REV 0x0201U /* Core revision r2p1 */ 90 #define __MPU_PRESENT 1 /* MPU present */ 91 #define __VTOR_PRESENT 1 /* VTOR present or not */ 92 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ 93 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 94 95 #ifdef __cplusplus 96 } 97 #endif 98 99 #include <core_cm3.h> /* Processor and core peripherals */ 100 101 #endif /* CMSDK_BEETLE_H */ 102
