Lines Matching full:interrupt

6   Cypress Interrupt Multiplex
14   4 interrupt sources by grouping intmux channels. These means that each byte
16   interrupt source in the multiplexer. The multiplexer is placed before
17   Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
20   On a general view, the below represents the Interrupt Multiplexer
23   The vector number selects the PSOC 6 peripheral interrupt source for the
31   In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
32   sources and the proper NVIC interrupt order. With that, the system configures
33   the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
38   The below fragment configure the GPIO Port 0 to generate an interrupt at
41   At psoc6.dtsi file the gpio_prt0 peripheral had the interrupt source 2:
47   In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
48   must be defined at gpio_prt0 node selecting the Interrupt Multiplex Channel.
52     interrupt-parent = <&intmux_ch20>;
59   These results in Cortex-M0+ NVIC line 20 handling PSOC 6 interrupt source 2.
60   The interrupt can be enabled/disabled at NVIC at line 20 as usual.
64   2) The interrupt sources are shared between Cortex-M0+/M4. This means, they
66   3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
67      at interrupt-parent properties.