Searched full:clk48_sel (Results 1 – 25 of 26) sorted by relevance
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| /Zephyr-latest/dts/arm/st/l4/ |
| D | stm32l496.dtsi | 25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
65 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
70 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l412.dtsi | 26 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
39 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l432.dtsi | 25 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
73 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l452.dtsi | 23 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l475.dtsi | 23 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
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| D | stm32l431.dtsi | 45 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
118 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l451.dtsi | 43 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
151 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l4p5.dtsi | 50 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
313 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
342 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
352 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l433.dtsi | 66 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| D | stm32l471.dtsi | 241 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
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| D | stm32l4.dtsi | 479 <&rcc STM32_SRC_MSI CLK48_SEL(3)>;
|
| /Zephyr-latest/dts/bindings/rng/ |
| D | st,stm32-rng.yaml | 19 <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
|
| /Zephyr-latest/boards/st/nucleo_u083rc/ |
| D | nucleo_u083rc.dts | 171 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
181 <&rcc STM32_SRC_HSI48 CLK48_SEL(1)>;
|
| /Zephyr-latest/boards/makerbase/mks_canable_v20/ |
| D | mks_canable_v20.dts | 77 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
| /Zephyr-latest/boards/st/stm32wb5mmg/ |
| D | stm32wb5mmg.dts | 42 clocks = <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32wb_clock.h | 87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) macro
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| D | stm32u0_clock.h | 87 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) macro
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| D | stm32g4_clock.h | 92 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) macro
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| D | stm32l4_clock.h | 93 #define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) macro
|
| /Zephyr-latest/boards/weact/stm32g431_core/ |
| D | weact_stm32g431_core.dts | 184 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;
|
| /Zephyr-latest/boards/st/nucleo_g431rb/ |
| D | nucleo_g431rb.dts | 97 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
| /Zephyr-latest/boards/st/stm32wb5mm_dk/ |
| D | stm32wb5mm_dk.dts | 83 clocks = <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
|
| /Zephyr-latest/boards/st/nucleo_wb55rg/ |
| D | nucleo_wb55rg.dts | 101 clocks = <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| /Zephyr-latest/dts/arm/st/wb/ |
| D | stm32wb.dtsi | 492 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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| /Zephyr-latest/dts/arm/st/g4/ |
| D | stm32g4.dtsi | 626 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
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