1/*
2 * Copyright (c) 2023 Andreas Sandberg
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <st/g4/stm32g431Xb.dtsi>
9#include <st/g4/stm32g431c(6-8-b)ux-pinctrl.dtsi>
10#include <zephyr/dt-bindings/usb-c/pd.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12
13/ {
14	model = "WeAct Studio STM32G431 Core Board";
15	compatible = "weact,stm32g431-core";
16
17	chosen {
18		zephyr,console = &usart2;
19		zephyr,shell-uart = &usart2;
20		zephyr,sram = &sram0;
21		zephyr,flash = &flash0;
22	};
23
24	aliases {
25		led0 = &led_0;
26		mcuboot-button0 = &button_0;
27		mcuboot-led0 = &led_0;
28		sw0 = &button_0;
29		sw1 = &button_1;
30		usbc-port0 = &usbc1;
31		watchdog0 = &iwdg;
32	};
33
34	leds {
35		compatible = "gpio-leds";
36		led_0: led0 {
37			gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
38			label = "Status LED";
39		};
40	};
41
42	gpio_keys {
43		compatible = "gpio-keys";
44		button_0: button0 {
45			label = "User";
46			gpios = <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
47			zephyr,code = <INPUT_KEY_0>;
48		};
49		button_1: button1 {
50			label = "Boot0";
51			gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>;
52			zephyr,code = <INPUT_KEY_1>;
53		};
54	};
55
56	vbus1: vbus {
57		compatible = "zephyr,usb-c-vbus-adc";
58		status = "disabled";
59		io-channels = <&adc2 12>;
60		output-ohms = <10000>;
61		full-ohms = <(100000 + 10000)>;
62	};
63
64	ports {
65		#address-cells = <1>;
66		#size-cells = <0>;
67
68		usbc1: usbc-port@1 {
69			compatible = "usb-c-connector";
70			status = "disabled";
71			reg = <1>;
72			tcpc = <&ucpd1>;
73			vbus = <&vbus1>;
74			data-role = "device";
75			power-role = "sink";
76			sink-pdos = <PDO_FIXED(5000, 100, PDO_FIXED_USB_COMM)>;
77		};
78	};
79};
80
81&clk_lsi {
82	status = "okay";
83};
84
85&clk_lse {
86	status = "okay";
87};
88
89&clk_hsi {
90	status = "disabled";
91};
92
93&clk_hse {
94	status = "okay";
95	clock-frequency = <DT_FREQ_M(8)>;
96};
97
98&rcc {
99	clocks = <&pll>;
100	clock-frequency = <DT_FREQ_M(144)>;
101	ahb-prescaler = <1>;
102	apb1-prescaler = <1>;
103	apb2-prescaler = <1>;
104};
105
106&pll {
107	status = "okay";
108	div-m = <2>;
109	mul-n = <72>;
110	div-p = <2>;
111	div-q = <6>;
112	div-r = <2>;
113	clocks = <&clk_hse>;
114};
115
116&rtc {
117	status = "okay";
118	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
119		 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
120};
121
122stm32_lp_tick_source: &lptim1 {
123	status = "okay";
124	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
125		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
126};
127
128&flash0 {
129	partitions {
130		compatible = "fixed-partitions";
131		#address-cells = <1>;
132		#size-cells = <1>;
133
134		/* 4KiB of storage at the end of the 128KiB FLASH */
135		storage_partition: partition@1f000 {
136			label = "storage";
137			reg = <0x0001f000 DT_SIZE_K(4)>;
138		};
139	};
140};
141
142&iwdg {
143	status = "okay";
144};
145
146&usart2 {
147	status = "okay";
148	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
149	pinctrl-names = "default";
150
151	current-speed = <115200>;
152};
153
154&adc2 {
155	pinctrl-0 = <&adc2_in12_pb2>;
156	pinctrl-names = "default";
157	st,adc-clock-source = "SYNC";
158	st,adc-prescaler = <4>;
159
160	#address-cells = <1>;
161	#size-cells = <0>;
162
163	channel@c {
164		reg = <12>;
165		zephyr,gain = "ADC_GAIN_1";
166		zephyr,reference = "ADC_REF_INTERNAL";
167		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
168		zephyr,resolution = <12>;
169		zephyr,vref-mv = <3300>;
170	};
171};
172
173&ucpd1 {
174	psc-ucpdclk = <1>;
175	hbitclkdiv = <27>;
176	pinctrl-0 = <&ucpd1_cc1_pb6 &ucpd1_cc2_pb4>;
177	pinctrl-names = "default";
178};
179
180zephyr_udc0: &usb {
181	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
182	pinctrl-names = "default";
183	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
184		 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;
185	status = "okay";
186};
187