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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_i2c_smb.h36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
50 #define MCHP_I2C_SMB_STS_LAB BIT(1)
51 #define MCHP_I2C_SMB_STS_AAS BIT(2)
[all …]
Dmec172x_ecia.h16 #define MCHP_FIRST_GIRQ_NOS 8u
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)
35 /* MEC172x implements 8 priority levels. ARM NVIC 0 = highest priority */
41 * External sources are grouped by 32-bit registers.
[all …]
Dmec172x_pcr.h56 * SLP_EN bit = 1 instructs HW to gate off clock tree to peripheral only if
57 * peripherals PCR CLK_REQ bit is 0.
58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
67 * SLEEP_ALL bit = 1.
76 * Write bit patterns to one or more of PCR RST_EN[0, 4] registers
84 #define MCHP_PCR_SLP(bitpos) BIT(bitpos)
88 #define MCHP_PCR_SYS_SLP_CTRL_SLP_HEAVY BIT(0)
89 #define MCHP_PCR_SYS_SLP_CTRL_SLP_ALL BIT(3)
91 * bit[8] can be used to prevent entry to heavy sleep unless the
93 * bit[8]==0 (POR default) system will allow entry to light or heavy
[all …]
Dmec172x_espi_vw.h13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
18 #define ESPI_M2SW0_MTOS_SRC_POS 8u
28 /* 32-bit word 1 (bits[63:32]) */
33 #define ESPI_M2SW1_SRC1_SEL_POS 8
40 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n) SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) SHLU32(((v) & 0xfu), ((n) * 8u))
43 /* 32-bit word 2 (bits[95:64]) */
44 #define ESPI_M2SW2_OFS 8u
[all …]
Dmec172x_p80bd.h15 /* HDATA - Write-Only 32-bit */
20 * EC-only Data/Attributes 16-bit
22 * b[15:8] = data attributes
27 #define MCHP_P80BD_ECDA_APOS 8
30 #define MCHP_P80BD_ECDA_LANE_POS 8
42 #define MCHP_P80BD_ECDA_NE BIT(12)
43 #define MCHP_P80BD_ECDA_OVR BIT(13)
44 #define MCHP_P80BD_ECDA_THR BIT(14)
49 #define MCHP_P80BD_CFG_FLUSH_FIFO BIT(0) /* WO */
50 #define MCHP_P80BD_CFG_SNAP_CLR BIT(1) /* WO */
[all …]
Dmec172x_qspi.h38 #define MCHP_QMSPI_TX_FIFO_LEN 8u
39 #define MCHP_QMSPI_RX_FIFO_LEN 8u
49 #define MCHP_QMSPI_EXE_OFS 8u
130 #define MCHP_QMSPI_M_ACTIVATE BIT(0)
131 #define MCHP_QMSPI_M_SRST BIT(1)
132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
135 #define MCHP_QMSPI_M_CPOL_POS 8u
137 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8)
[all …]
/Zephyr-latest/drivers/display/
DKconfig.stm32_ltdc28 One pixel consists of 8-bit alpha, 8-bit red, 8-bit green and 8-bit blue value
34 One pixel consists of 8-bit red, 8-bit green and 8-bit blue value
40 One pixel consists of 5-bit red, 6-bit green and 5-bit blue value
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h34 #define RDR_MASK_RDAT GENMASK(8, 0)
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h18 ((flag_u32) >> ROUND_DOWN(LOG2((flag_u32)), 8))
28 #define MCP251XFD_TEF_FIFO_ITEM_SIZE 8
29 #define MCP251XFD_TX_QUEUE_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
32 #define MCP251XFD_RX_FIFO_ITEM_SIZE (4 + 8 + MCP251XFD_PAYLOAD_SIZE)
34 #define MCP251XFD_RX_FIFO_ITEM_SIZE (8 + MCP251XFD_PAYLOAD_SIZE)
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
[all …]
/Zephyr-latest/drivers/spi/
Dspi_pw.h41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
72 #define PW_SPI_CTRL1_TIE_BIT BIT(1)
[all …]
Dspi_andes_atcspi200.h42 #define TFMAT_DATA_LEN_OFFSET (8)
44 #define TFMAT_CPHA_MSK BIT(0)
45 #define TFMAT_CPOL_MSK BIT(1)
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_LSB_MSK BIT(3)
48 #define TFMAT_DATA_MERGE_MSK BIT(7)
49 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
66 #define IEN_RX_FIFO_MSK BIT(2)
67 #define IEN_TX_FIFO_MSK BIT(3)
68 #define IEN_END_MSK BIT(4)
[all …]
Dspi_dw.h26 typedef void (*spi_dw_set_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
27 typedef void (*spi_dw_clear_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
28 typedef int (*spi_dw_test_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
79 static void aux_reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_set_bit() argument
81 sys_io_set_bit(addr + off/4, bit); in aux_reg_set_bit()
84 static void aux_reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_clear_bit() argument
86 sys_io_clear_bit(addr + off/4, bit); in aux_reg_clear_bit()
89 static int aux_reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off) in aux_reg_test_bit() argument
91 return sys_io_test_bit(addr + off/4, bit); in aux_reg_test_bit()
99 case 8: in reg_read()
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h40 IPC_EVENT_BIT(8) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
57 [5] = BIT(5),
58 [6] = BIT(6),
59 [7] = BIT(7),
60 [8] = BIT(8),
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_enc424j600_priv.h136 #define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00)
137 #define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01)
138 #define ENC424J600_PSFR_PHANA (BIT(8) | 0x04)
139 #define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05)
140 #define ENC424J600_PSFR_PHANE (BIT(8) | 0x06)
141 #define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11)
142 #define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B)
143 #define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F)
195 #define ENC424J600_MICMD_MIIRD BIT(0)
197 #define ENC424J600_MISTAT_BUSY BIT(0)
[all …]
Deth_dwmac_priv.h97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
105 #define MAC_CONF_WD BIT(19)
106 #define MAC_CONF_BE BIT(18)
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
[all …]
/Zephyr-latest/drivers/sdhc/
Drcar_mmc_registers.h9 #include <zephyr/sys/util_macro.h> /* for BIT macro */
16 #define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
17 #define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */
18 #define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
19 #define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */
20 #define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
21 #define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
22 #define RCAR_MMC_CMD_RSP_NONE (3 << 8) /* response: none */
23 #define RCAR_MMC_CMD_RSP_R1 (4 << 8) /* response: R1, R5, R6, R7 */
24 #define RCAR_MMC_CMD_RSP_R1B (5 << 8) /* response: R1b, R5b */
[all …]
/Zephyr-latest/subsys/fs/ext2/
Dext2_bitmap.c20 LOG_DBG("Setting %d bit in bitmap", index); in ext2_bitmap_set()
22 uint32_t idx = index / 8; in ext2_bitmap_set()
23 uint32_t off = index % 8; in ext2_bitmap_set()
30 __ASSERT((bm[idx] & BIT(off)) == 0, "Bit %d set in bitmap", index); in ext2_bitmap_set()
33 bm[idx] |= BIT(off); in ext2_bitmap_set()
41 LOG_DBG("Unsetting %d bit in bitmap", index); in ext2_bitmap_unset()
43 uint32_t idx = index / 8; in ext2_bitmap_unset()
44 uint32_t off = index % 8; in ext2_bitmap_unset()
51 __ASSERT(bm[idx] & BIT(off), "Bit %d not set in bitmap", index); in ext2_bitmap_unset()
54 bm[idx] &= ~BIT(off); in ext2_bitmap_unset()
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi43 0x00f01660 8>; /* GPCR */
44 ngpios = <8>;
57 wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(0)
58 BIT(1) BIT(2) BIT(3) BIT(4) >;
69 0x00f01668 8>; /* GPCR */
83 wuc-mask = <BIT(5) BIT(6) BIT(4) BIT(7)
84 BIT(6) BIT(0) BIT(1) 0 >;
95 0x00f01670 8>; /* GPCR */
96 ngpios = <8>;
109 wuc-mask = <BIT(5) BIT(3) BIT(7) BIT(4)
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v1.h37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
39 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
47 #define SSCR0_ACS BIT(30)
48 #define SSCR0_MOD BIT(31)
[all …]
Dssp_regs_v2.h38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
40 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
48 #define SSCR0_ACS BIT(30)
49 #define SSCR0_MOD BIT(31)
[all …]
Dssp_regs_v3.h24 #define I2SIPCMC 8
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
47 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8)
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
55 #define SSCR0_EFRDC BIT(27)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml22 3.125 - 25/8 - 320ms
58 1 sample, 16-bit, 2.64 Pa
59 2 samples, 17-bit, 1.32 Pa
60 4 samples, 18-bit, 0.66 Pa (default; chip reset value)
61 8 samples, 19-bit, 0.33 Pa
62 16 samples, 20-bit, 0.17 Pa
63 32 Samples, 21-bit, 0.085 Pa
69 - 8
78 1 sample, 16-bit, .0050 C (default; chip reset value)
79 2 samples, 17-bit, .0025 C
[all …]
Dbosch,bmp390.yaml23 3.125 - 25/8 - 320ms
59 1 sample, 16-bit, 2.64 Pa
60 2 samples, 17-bit, 1.32 Pa
61 4 samples, 18-bit, 0.66 Pa (default; chip reset value)
62 8 samples, 19-bit, 0.33 Pa
63 16 samples, 20-bit, 0.17 Pa
64 32 Samples, 21-bit, 0.085 Pa
70 - 8
79 1 sample, 16-bit, .0050 C (default; chip reset value)
80 2 samples, 17-bit, .0025 C
[all …]
/Zephyr-latest/modules/lvgl/
Dlvgl_display_mono.c18 uint8_t bit; in set_px_at_pos() local
22 buf = dst_buf + x + y / 8 * width; in set_px_at_pos()
25 bit = 7 - y % 8; in set_px_at_pos()
27 bit = y % 8; in set_px_at_pos()
30 buf = dst_buf + x / 8 + y * width / 8; in set_px_at_pos()
33 bit = 7 - x % 8; in set_px_at_pos()
35 bit = x % 8; in set_px_at_pos()
40 *buf |= BIT(bit); in set_px_at_pos()
42 *buf &= ~BIT(bit); in set_px_at_pos()
54 *px_map += 8; in lvgl_transform_buffer()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpmc_interface.h29 * Some commands require additional information which is passed into this 8 bit field.
31 #define CW_PMC_IPC_PARAM1 GENMASK(15, 8)
34 * Some commands require additional information which is passed into this 8 bit field.
39 * Some commands require additional information which is passed into this 4 bit field.
49 * busy - The run/busy bit can only be set by the requesting agent and can only be cleared by the
50 * responding agent. When this bit is set it will prompt the PMC to execute the command placed in
55 #define CW_PMC_IPC_BUSY BIT(31)
61 * No operation - PMC FW will clear the run / busy bit and return a success response
73 * HP-SRAM reporting is defined as 10-bit field span across Parameter 1 and 2, unit is 32 KB.
80 #define CW_PMC_IPC_SRAM_USED_BANKS GENMASK(17, 8)
[all …]

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