Lines Matching +full:8 +full:bit

13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
18 #define ESPI_M2SW0_MTOS_SRC_POS		8u
28 /* 32-bit word 1 (bits[63:32]) */
33 #define ESPI_M2SW1_SRC1_SEL_POS		8
40 #define ESPI_M2SW1_SRC_SEL_POS(n)	((n) * 8u)
41 #define ESPI_M2SW1_SRC_SEL_MASK(n)	SHLU32(0xfu, ((n) * 8u))
42 #define ESPI_M2SW1_SRC_SEL_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))
43 /* 32-bit word 2 (bits[95:64]) */
44 #define ESPI_M2SW2_OFS			8u
48 #define ESPI_M2SW2_SRC1_POS		8u
55 #define ESPI_M2SW2_SRC_POS(n)		((n) * 8u)
56 #define ESPI_M2SW2_SRC_MASK(n)		SHLU32(0xfu, ((n) * 8u))
57 #define ESPI_M2SW2_SRC_VAL(n, v)	SHLU32(((v) & 0xfu), ((n) * 8u))
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
78 /* 32-bit word 0 (bits[31:0]) */
82 #define ESPI_S2MW0_STOM_POS		8u
83 #define ESPI_S2MW0_STOM_SRC_POS		8u
96 #define ESPI_S2MW0_CHG0			BIT(ESPI_S2MW0_CHG0_POS)
98 #define ESPI_S2MW0_CHG1			BIT(ESPI_S2MW0_CHG1_POS)
100 #define ESPI_S2MW0_CHG2			BIT(ESPI_S2MW0_CHG2_POS)
102 #define ESPI_S2MW0_CHG3			BIT(ESPI_S2MW0_CHG3_POS)
111 /* 32-bit word 1 (bits[63:32]) */
114 #define ESPI_S2MW1_SRC0			BIT(ESPI_S2MW1_SRC0_POS)
115 #define ESPI_S2MW1_SRC1_POS		8u
116 #define ESPI_S2MW1_SRC1			BIT(ESPI_S2MW1_SRC1_POS)
118 #define ESPI_S2MW1_SRC2			BIT(ESPI_S2MW1_SRC2_POS)
120 #define ESPI_S2MW1_SRC3			BIT(ESPI_S2MW1_SRC3_POS)
150 #define MSVW_SRC0_OFS		8u
165 /* Master-to-Slave Virtual Wire 96-bit register */
167 #define MEC_MSVW_SRC1_IRQ_SEL_POS	8u
193 	((uint32_t)(isel) << ((src) * 8u))
196 #define MEC_MSVW_SRC1_POS	8u
202 #define MEC_MSVW_SRC0_MASK	BIT(0)
203 #define MEC_MSVW_SRC1_MASK	BIT(8)
204 #define MEC_MSVW_SRC2_MASK	BIT(16)
205 #define MEC_MSVW_SRC3_MASK	BIT(24)
212 	((uint32_t)(val & 0x01u) << ((src) * 8u))
214 /* Slave-to-Master Virtual Wire 64-bit register */
282 /** @brief eSPI 96-bit Host-to-Target Virtual Wire register */
291 /** @brief eSPI 96-bit Host-to-Target Virtual Wire register as bytes */
321 /** @brief eSPI 64-bit Target-to-Host Virtual Wire register */
330 /** @brief eSPI 64-bit Target-to-Host Virtual Wire register as bytes */
332 	volatile uint8_t THVWB[8];