26 typedef void (*spi_dw_set_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
27 typedef void (*spi_dw_clear_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
28 typedef int (*spi_dw_test_bit_t)(uint8_t bit, mm_reg_t addr, uint32_t off);
79 static void aux_reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in aux_reg_set_bit()  argument
81 	sys_io_set_bit(addr + off/4, bit);  in aux_reg_set_bit()
84 static void aux_reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in aux_reg_clear_bit()  argument
86 	sys_io_clear_bit(addr + off/4, bit);  in aux_reg_clear_bit()
89 static int aux_reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in aux_reg_test_bit()  argument
91 	return sys_io_test_bit(addr + off/4, bit);  in aux_reg_test_bit()
99 	case 8:  in reg_read()
113 	case 8:  in reg_write()
124 static void reg_set_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in reg_set_bit()  argument
126 	sys_set_bit(addr + off, bit);  in reg_set_bit()
129 static void reg_clear_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in reg_clear_bit()  argument
131 	sys_clear_bit(addr + off, bit);  in reg_clear_bit()
134 static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)  in reg_test_bit()  argument
136 	return sys_test_bit(addr + off, bit);  in reg_test_bit()
185 #define DW_SPI_CTRLR0_TMOD_SHIFT	(8)
190 #define DW_SPI_CTRLR0_SCPH_BIT		(8)
197 #define DW_SPI_CTRLR0_SCPH		BIT(DW_SPI_CTRLR0_SCPH_BIT)
198 #define DW_SPI_CTRLR0_SCPOL		BIT(DW_SPI_CTRLR0_SCPOL_BIT)
199 #define DW_SPI_CTRLR0_SRL		BIT(DW_SPI_CTRLR0_SRL_BIT)
200 #define DW_SPI_CTRLR0_SLV_OE		BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
211 /* 0x38 represents the bits 8, 16 and 32. Knowing that 24 is bits 8 and 16
212  * These are the bits were when you divide by 8, you keep the result as it is.
217 					 (((__bpw) / 8) + 1) :		\
218 					 ((__bpw) / 8))
240 #define DW_SPI_IMR_TXEIM		BIT(DW_SPI_IMR_TXEIM_BIT)
241 #define DW_SPI_IMR_TXOIM		BIT(DW_SPI_IMR_TXOIM_BIT)
242 #define DW_SPI_IMR_RXUIM		BIT(DW_SPI_IMR_RXUIM_BIT)
243 #define DW_SPI_IMR_RXOIM		BIT(DW_SPI_IMR_RXOIM_BIT)
244 #define DW_SPI_IMR_RXFIM		BIT(DW_SPI_IMR_RXFIM_BIT)
245 #define DW_SPI_IMR_MSTIM		BIT(DW_SPI_IMR_MSTIM_BIT)
260 /* ICR Bit */
301 DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
302 DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 8)
303 DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)