Lines Matching +full:8 +full:bit
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
59 /* SSP Baud rate sscr0[19:8] */
66 /* [19:8] 12 bits */
67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
72 #define PW_SPI_CTRL1_TIE_BIT BIT(1)
73 #define PW_SPI_CTRL1_LBM_BIT BIT(2)
74 #define PW_SPI_CTRL1_SPO_BIT BIT(3)
75 #define PW_SPI_CTRL1_SPH_BIT BIT(4)
76 #define PW_SPI_CTRL1_IFS_BIT BIT(16)
77 #define PW_SPI_CTRL1_TINTE_BIT BIT(19)
78 #define PW_SPI_CTRL1_RSRE_BIT BIT(20)
79 #define PW_SPI_CTRL1_TSRE_BIT BIT(21)
80 #define PW_SPI_CTRL1_TRAIL_BIT BIT(22)
81 #define PW_SPI_CTRL1_RWOT_BIT BIT(23)
87 #define PW_SPI_SSSR_TNF_BIT BIT(2)
88 #define PW_SPI_SSSR_RNE_BIT BIT(3)
89 #define PW_SPI_SSSR_BSY_BIT BIT(4)
90 #define PW_SPI_SSSR_TFS_BIT BIT(5)
91 #define PW_SPI_SSSR_RFS_BIT BIT(6)
92 #define PW_SPI_SSSR_ROR_BIT BIT(7)
93 #define PW_SPI_SSSR_PINT_BIT BIT(18)
94 #define PW_SPI_SSSR_TINT_BIT BIT(19)
95 #define PW_SPI_SSSR_TUR_BIT BIT(21)
105 /* SPI Tx FIFO Lower Water Mark[13:8] */
106 #define PW_SPI_SITF_LWM_2_ENTRY (BIT(0) << 8)
107 #define PW_SPI_SITF_LWM_3_ENTRY (BIT(1) << 8)
108 #define PW_SPI_SITF_LWM_4_ENTRY ((BIT(1) | BIT(0)) << 8)
124 /* SPI Rx FIFO Level RITF[13:8] */
125 #define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8)
131 #define PW_SPI_SITF_LOW_WM_DFLT BIT(PW_SPI_SITF_LWMTF_SHIFT)
136 #define PW_SPI_CLKS_EN_BIT BIT(0)
137 #define PW_SPI_CLKS_MVAL BIT(1)
138 #define PW_SPI_CLKS_NVAL BIT(16)
139 #define PW_SPI_CLKS_UPDATE_BIT BIT(31)
172 #define PW_SPI_CS_CTRL_SW_MODE BIT(0)
173 #define PW_SPI_CS_HIGH BIT(1)
177 #define PW_SPI_CS0_SELECT (~(BIT(PW_SPI_CS_EN_SHIFT)))
178 #define PW_SPI_CS1_SELECT BIT(PW_SPI_CS_EN_SHIFT)
181 #define PW_SPI_WIDTH_8BITS 8