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/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
126 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
128 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dsoc.c57 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
71 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
73 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
77 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
79 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
83 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
85 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
89 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
91 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
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/Zephyr-latest/soc/espressif/common/
DKconfig.esptool88 bool "120 MHz"
92 - Flash 120 MHz SDR mode is stable.
93 - Flash 120 MHz DDR mode is an experimental feature, it works when
102 bool "80 MHz"
104 bool "60 MHz"
106 bool "40 MHz"
108 bool "26 MHz"
111 bool "20 MHz"
119 This is an invisible item, used to define the targets that defaults to use 80MHz Flash SPI speed.
123 # On some of the ESP chips, max boot frequency would be equal to (or even lower than) 80m.
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/Zephyr-latest/include/zephyr/dt-bindings/ethernet/
Dxlnx_gem.h28 #define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or IOU_SWITCH_CLK < 20 MHz */
29 #define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or IOU_SWITCH_CLK 20 - 40 MHz */
30 #define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or IOU_SWITCH_CLK 40 - 80 MHz */
31 #define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x or IOU_SWITCH_CLK 80 - 120 MHz */
32 #define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x or IOU_SWITCH_CLK 120 - 160 MHz */
33 #define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x or IOU_SWITCH_CLK 160 - 240 MHz */
34 #define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x or IOU_SWITCH_CLK 240 - 320 MHz */
35 #define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x or IOU_SWITCH_CLK 320 - 540 MHz */
/Zephyr-latest/drivers/watchdog/
DKconfig.cc32xx19 80 Mhz: 0xFFFFFFFF / (80e9 / 1000)
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/drivers/ieee802154/
DKconfig.mcr20a33 bool "32 MHz"
36 bool "16 MHz"
39 bool "8 MHz"
42 bool "4 MHz"
45 bool "1 MHz"
68 default 80
/Zephyr-latest/tests/drivers/can/timing/
DKconfig33 - 20 MHz
34 - 40 MHz
35 - 80 MHz
/Zephyr-latest/drivers/clock_control/
Dclock_stm32l4_l5_wb_wl.c74 /* set power boost mode for sys clock greater than 80MHz */ in config_pll_sysclock()
75 if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) { in config_pll_sysclock()
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,imx8m-pinctrl.yaml90 011 75_OHM — 75 Ohm @3.3V, 70 Ohm @2.5V, 60 Ohm @1.8V, 80 Ohm @1.2V
91 100 85_OHM — 85 Ohm @3.3V, 80 Ohm @2.5V, 75 Ohm @1.8V, 90 Ohm @1.2V
105 00 SLOW — Slow Frequency Slew Rate (50Mhz)
106 01 MEDIUM — Medium Frequency Slew Rate (100Mhz)
107 10 FAST — Fast Frequency Slew Rate (150Mhz)
108 11 MAX — Max Frequency Slew Rate (200Mhz)
/Zephyr-latest/dts/bindings/clock/
Dst,stm32l4-pll-clock.yaml11 an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
23 The PLL output frequency must not exceed 80 MHz.
62 Main PLL division factor for PLL48M1CLK (48 MHz clock).
Dst,stm32f4-pll-clock.yaml8 input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
19 The PLL output frequency must not exceed 80 MHz.
Dst,stm32h7-pll-clock.yaml11 an input frequency from 1 to 16 MHz. PLLM factor is used to set the input
23 The PLL output frequency must not exceed 80 MHz.
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
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Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
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/Zephyr-latest/soc/atmel/sam/sam4l/
Dsoc.h73 * Internal 80 MHz RC oscillator
74 * Internal 4-8-12 MHz RCFAST oscillator
75 * Internal 1 MHz RC oscillator
91 * 80 MHz RC oscillator
92 * 4-8-12 MHz RC oscillator
93 * 1 MHz RC oscillator
/Zephyr-latest/boards/shields/lcd_par_s035/
Dlcd_par_s035_8080.overlay40 /* Baud rate on each pin is 1MHz */
46 frmctl1 = [80 10];
49 pwr1 = [80 64];
/Zephyr-latest/boards/makerbase/mks_canable_v20/
Dmks_canable_v20.dts39 /* Internal 16 MHz clock used to drive PLL */
44 /* Internal 48 MHz clock used to drive USB */
48 /* Adjust the pll for a SYSTEM Clock of 160 MHz */
51 mul-n = <80>;
/Zephyr-latest/tests/drivers/flash/common/boards/
Dnrf52840dk_spi_nor_wp_hold.overlay42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
Dnrf52840dk_spi_nor.overlay42 spi-max-frequency = <8000000>; // chip supports 80Mhz, SPI0 supports 8MHz
/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
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/Zephyr-latest/tests/kernel/timer/starve/
DREADME.txt26 Systems that use a 32-bit counter of 80 MHz ticks would fail after
/Zephyr-latest/boards/st/nucleo_l412rb_p/doc/
Dindex.rst28 - 24 MHz HSE
54 - 79 |micro| A/MHz run mode (LDO Mode)
55 - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode)
61 …de| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and…
64 - 1.25 DMIPS/MHz (Drystone 2.1)
65 - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz)
74 - 4 to 48 MHz crystal oscillator
76 - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
78 …- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0…
79 - Internal 48 MHz with clock recovery
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/Zephyr-latest/tests/boards/espressif/rtc_clk/
DREADME.rst55 Testing CPU frequency: 80 MHz
56 Testing CPU frequency: 160 MHz
57 Testing CPU frequency: 240 MHz
61 Testing CPU frequency: 40 MHz
62 Testing CPU frequency: 20 MHz
63 Testing CPU frequency: 10 MHz
64 Testing CPU frequency: 5 MHz
68 Testing RTC FAST CLK freq: 20000000 MHz
69 Testing RTC FAST CLK freq: 17500000 MHz
73 Testing RTC SLOW CLK freq: 136000 MHz
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