Home
last modified time | relevance | path

Searched +full:7 +full:- +full:pin (Results 1 – 25 of 673) sorted by relevance

12345678910>>...27

/Zephyr-latest/drivers/pinctrl/
Dpinctrl_b91.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
[all …]
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
22 /* gpio port control register (byte mapping to pin) */
46 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
47 * (bit mapping to pin)
50 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
53 * KSO push-pull/open-drain bit of KSO[15:0] control register
58 * KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
74 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
75 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
76 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
[all …]
Dpinctrl_ene_kb1200.c4 * SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h>
42 * b[7:5] = pin bank
43 * b[4:0] = pin position in bank
48 #define ENE_KB1200_PINMUX_PORT(p) FIELD_GET(GENMASK(7, 5), p)
50 #define ENE_KB1200_PINMUX_PORT_PIN(p) FIELD_GET(GENMASK(7, 0), p)
63 uint32_t pin = (uint32_t)ENE_KB1200_PINMUX_PIN(gpio); in kb1200_config_pin() local
68 return -EINVAL; in kb1200_config_pin()
72 WRITE_BIT(gpio_regs->GPIOFS, pin, 0); in kb1200_config_pin()
74 func -= 1; /*for change to GPIOALT setting value*/ in kb1200_config_pin()
[all …]
/Zephyr-latest/dts/bindings/gpio/
Ddigilent,pmod.yaml2 # SPDX-License-Identifier: Apache-2.0
8 through 3 correspond to IO1 through IO4, and parent pins 4 through 7
9 correspond to IO5 through IO8, as depicted below for a 12-pin connector.
11 12-pin Pmod interface:
16 3 IO4 IO8 7
17 - GND GND -
18 - VDD VDD -
20 This binding can also be used with the 6-pin Pmod connector variant which
21 is a proper subset of the 12-pin connector. In that case parent pins 4
22 through 7 are omitted from the GPIO nexus node, resulting in a mapping
[all …]
Datmel-xplained-header.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained layout provide a standard 10 pin header. A board can have
12 every pin can be defined as general purpose GPIO.
29 https://www.microchip.com/development-tools/xplained-boards
30 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
36 Bind Pin Name Pin Pin Pin Name Bind
40 6 SPI(MISO) 7 8 SPI(SCK) 7
43 compatible: "atmel-xplained-header"
45 include: [gpio-nexus.yaml, base.yaml]
Dseeed-xiao-header.yaml4 # SPDX-License-Identifier: Apache-2.0
12 Proceeding counter-clockwise:
13 * A 7-pin Digital/Analog Input header. This has input signals
15 * An 7-pin header Power and Digital/Analog Input header. This
17 top through 7 at the bottom.
22 0 D0 5V -
23 1 D1 GND -
24 2 D2 3V3 -
28 6 D6 D7 7
31 compatible: "seeed,xiao-gpio"
[all …]
Datmel-xplained-pro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
40 6 IRQ/GPIO3 9 10 SPI(CS1)/GPIO4 7
47 compatible: "atmel-xplained-pro-header"
[all …]
Dnxp,lcd-8080.yaml2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
12 Pin Number Usage
19 7 LCD touch controller I2C SCL
24 12 LCD 8080 interface D/C pin
25 13 LCD 8080 interface CS pin
26 14 LCD 8080 interface WR pin
27 15 LCD 8080 interface RD pin
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dambiq,apollo4-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Ambiq Apollo4 pin controller is a node responsible for controlling
6 pin function selection and pin properties, such as routing a UART0 TX
7 to pin 60 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
23 /* include pre-defined combinations for the SoC variant used by the board */
24 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
33 input-enable;
38 The 'uart0_default' child node encodes the pin configurations for a
[all …]
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
[all …]
Dnxp,s32ze-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
[all …]
/Zephyr-latest/samples/drivers/i2c/rtio_loopback/boards/
Db_u585i_iot02a.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
7 * i2c1 PB9 CN3:10 PB8 CN3:7
8 * i2c2 PH5 CN2:10 PH4 CN2:7
10 * Short Pin PB9 to PH5, and PB8 to PH4, for the test to pass.
15 i2c-controller = &i2c1;
16 i2c-controller-target = &i2c2;
/Zephyr-latest/drivers/gpio/
Dgpio_kscan_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
[all …]
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
37 /* gpio port control register (byte mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dti-cc32xx-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
[all …]
Dgecko-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
[all …]
Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
[all …]
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2024 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
[all …]
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Db_u585i_iot02a.overlay1 /* SPDX-License-Identifier: Apache-2.0 */
6 * Pin Hdr Pin Hdr
7 * i2c1 PB9 CN3:10 PB8 CN3:7
8 * i2c2 PH5 CN2:10 PH4 CN2:7
10 * Short Pin PB9 to PH5, and PB8 to PH4, for the test to pass.
13 /delete-node/ &eeprom0;
17 compatible = "zephyr,i2c-target-eeprom";
25 compatible = "zephyr,i2c-target-eeprom";
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-rcar-common.h2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
27 /* Arbitrary number to encode non capable gpio pin */
31 * @brief Utility macro to encode a GPIO capable pin
34 * @param pin the pin within the GPIO bank (0..31)
36 #define RCAR_GP_PIN(bank, pin) (((bank) * 32U) + (pin)) argument
39 * @brief Utility macro to encode a non capable GPIO pin
41 * @param pin the encoded pin number
43 #define RCAR_NOGP_PIN(pin) (PIN_NOGPSR_START + pin) argument
80 #define IP0SR7(shift, func) IPnSR(0, 7, shift, func)
[all …]
/Zephyr-latest/drivers/smbus/
Dintel_pch_smbus.h7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */
32 #define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */
51 #define PCH_SMBUS_HCTL_CMD_BLOCK_PROC (7 << 2) /* Block Process cmd */
59 #define PCH_SMBUS_HCTL_PEC_EN BIT(7) /* Enable PEC */
67 #define PCH_SMBUS_TSA_ADDR_MASK GENMASK(7, 1) /* Address mask */
69 /* Set 7-bit address */
70 #define PCH_SMBUS_TSA_ADDR_SET(addr) (((addr) & BIT_MASK(7)) << 1)
73 #define PCH_SMBUS_TSA_ADDR_GET(reg) ((reg >> 1) & BIT_MASK(7))
[all …]
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
134 bool "Move Read-Only Data in Flash to PSRAM"
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149 If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
153 menu "PSRAM clock and cs IO for ESP32-DOWD"
161 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dst,ism330dhcx-common.yaml2 # SPDX-License-Identifier: Apache-2.0
5 When setting the accel-odr and gyro-odr properties in a .dts or .dtsi file you may include
9 #include <zephyr/dt-bindings/sensor/ism330dhcx.h>
14 accel-odr = <ISM330DHCX_DT_ODR_104Hz>;
15 gyro-odr = <ISM330DHCX_DT_ODR_104Hz>;
18 include: sensor-device.yaml
21 drdy-gpios:
22 type: phandle-array
24 DRDY gpio pin
26 This pin defaults to active high when produced by the sensor.
[all …]
Dst,lis2dux12-common.yaml2 # SPDX-License-Identifier: Apache-2.0
5 When setting the odr, power-mode, and range properties in a .dts or .dtsi file you may include
8 #include <zephyr/dt-bindings/sensor/st_lis2dux12.h>
11 power-mode = <LIS2DUX12_OPER_MODE_LOW_POWER>;
16 include: sensor-device.yaml
19 int1-gpios:
20 type: phandle-array
22 INT1 pin
24 This pin defaults to active high when produced by the sensor.
27 int2-gpios:
[all …]
/Zephyr-latest/tests/drivers/pinctrl/gd32/src/
Dmain_af.c3 * SPDX-License-Identifier: Apache-2.0
9 /* pin configuration for test device */
17 pinctrl_soc_pin_t pin; in ZTEST() local
19 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
21 scfg = &pcfg->states[0]; in ZTEST()
23 zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT); in ZTEST()
24 zassert_equal(scfg->pin_cnt, 12U); in ZTEST()
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
[all …]

12345678910>>...27